參數(shù)資料
型號： AD9983AKSTZ-170
廠商： Analog Devices Inc
文件頁數(shù)： 17/44頁
文件大?。?/td> 0K
描述： IC DISPLAY 8BIT 170MSPS 80LQFP
標準包裝： 1
應用： 視頻
接口： 模擬
電源電壓： 1.7 V ~ 3.47 V
封裝/外殼： 80-LQFP
供應商設備封裝： 80-LQFP（14x14）
包裝： 管件
安裝類型： 表面貼裝
AD9983A
Rev. 0 | Page 24 of 44
Hex
Address
Read/Write,
Read Only
Bits
Default
Value
Register Name
Description
0x12
R/W
7
0*** ****
Hsync Control
Active Hsync Override.
0 = The chip determines the active Hsync source
1 = The active Hsync source is set by Reg. 0x12, Bit 6
6
*0** ****
Selects the source of the Hsync for PLL and sync processing. This bit is
used only if Reg. 0x12, Bit 7 is set to 1 or if both syncs are active.
0 = Hsync is from HSYNCx input pin
1 = Hsync is from SOGINx
5
**0* ****
Hsync Input Polarity Override.
0 = The chip selects the Hsync input polarity
1 = The polarity of the input Hsync is controlled by Reg. 0x12, Bit 4
This applies to both HSYNC0 and HSYNC1.
4
***1 ****
Hsync Input Polarity. This bit is used only if Reg. 0x12, Bit 5 is set to 1.
0 = Active low input Hsync
1 = Active high input Hsync
3
**** 1***
Sets the polarity of the Hsync output signal.
0 = Active low Hsync output
1 = Active high Hsync output
0x13
R/W
7:0
0010 0000
Hsync Duration
Sets the number of pixel clocks that HSOUT is active.
0x14
R/W
7
0*** ****
Vsync Control
Active Vsync Override.
0 = The chip determines the active Vsync source
1 = The active Vsync source is set by Reg. 0x14, Bit 6
6
*0** ****
Selects the source of Vsync for the sync processing. This bit is used
only if Reg. 0x14, Bit 7 is set to 1.
0 = Vsync is from the Vsync input pin
1 = Vsync is from the sync separator
5
**0* ****
Vsync Input Polarity Override. This applies to both VSYNC0 and
VSYNC1.
0 = The chip selects the input Vsync polarity
1 = The polarity of the input Vsync is set by Reg. 0x14, Bit 4
4
***1 ****
Vsync Input Polarity. This bit is used only if Reg. 0x14, Bit 5 is set to 1.
0 = Active low input Vsync
1 = Active high input Vsync
3
**** 1***
Sets the polarity of the output Vsync signal.
0 = Active low output Vsync
1 = Active high output Vsync
2
**** *0**
Vsync Filter Enable. This needs to be enabled when using the
Hsync to Vsync counter.
0 = The Vsync filter is disabled
1 = The Vsync filter is enabled
1
**** **0*
Enables the Vsync duration block. This is designed to be used with
the Vsync filter.
0 = Vsync output duration is unchanged
1 = Vsync output duration is set by Reg. 0x15
0x15
R/W
7:0
0000 1010
Vsync Duration
Sets the number of Hsyncs that Vsync out is active. This is only
used if Reg. 0x14, Bit 1 is set to 1.
0x16
R/W
7:0
0000 0000
Precoast
The number of Hsync periods to coast prior to Vsync.
0x17
R/W
7:0
0000 0000
Postcoast
The number of Hsync periods to coast after Vsync.
0x18
R/W
7
0*** ****
Coast and Clamp
Control
Coast Source. Selects the source of the coast signal.
0 = Using internal coast generated from Vsync
1 = Using external coast signal from external COAST pin
6
*0** ****
Coast Polarity Override.
0 = The chip selects the external coast polarity
1 = The polarity of the external coast signal is set by Reg. 0x18, Bit 5
5
**1* ****
Coast Input Polarity. This bit is used only if Reg. 0x18, Bit 6 is set to 1.
0 = Active low external coast
1 = Active high external coast
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