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| 型號： | AD9983AKSTZ-170 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 16/44頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DISPLAY 8BIT 170MSPS 80LQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 應(yīng)用： | 視頻 |
| 接口： | 模擬 |
| 電源電壓： | 1.7 V ~ 3.47 V |
| 封裝/外殼： | 80-LQFP |
| 供應(yīng)商設(shè)備封裝： | 80-LQFP（14x14） |
| 包裝： | 管件 |
| 安裝類型： | 表面貼裝 |
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AD9983A
Rev. 0 | Page 23 of 44
2-WIRE SERIAL REGISTER MAP
The AD9983A is initialized and controlled by a set of registers that determine the operating modes. An external controller is employed to
write and read the control registers through the 2-wire serial interface port.
Table 14. Control Register Map
Hex
Address
Read/Write,
Read Only
Bits
Default
Value
Register Name
Description
0x00
RO
7:0
Chip Revision
An 8-bit register that represents the silicon revision level.
0x01
R/W
7:0
0110 1001
PLL Div MSB
This register is for Bits [11:4] of the PLL divider. Larger values mean
the PLL operates at a faster rate. This register should be loaded first
whenever a change is needed. (This will give the PLL more time to
0x02
R/W
7:4
1101 ****
PLL Div LSB
LSBs of the PLL Divider Word. Links to the PLL Div MSB to make a
12-bit register.1
0x03
R/W
7:6
01** ****
VCO/CPMP
VCO Range. Selects VCO frequency range. (See PLL section).
5:3
**00 1***
Charge Pump Current. Varies the current that drives the low-pass
filter. (See PLL section).
2
**** *0**
External Clock Enable.
0x04
R/W
7:3
1000 0***
Phase Adjust
ADC Clock Phase Adjustment. Larger values mean more delay.
(1 LSB = T/32).
0x05
R/W
6:0
*100 0000
Red Gain MSB
7-Bit Red Channel Gain Control. Controls the ADC input range
(contrast) of each respective channel. Bigger values give less
contrast.2
0x06
R/W
7:0
0000 0000
Must be written to 0x00 following a write of Reg. 0x05 for proper
operation.
0x07
R/W
6:0
*100 0000
Green Gain MSB
7-Bit Green Channel Gain Control. Controls the ADC input range
(contrast) of each respective channel. Bigger values give less
contrast.2
0x08
R/W
7:0
0000 0000
Must be written to 0x00 following a write of Reg. 0x07 for proper
operation.
0x09
R/W
6:0
*100 0000
Blue Gain MSB
7-Bit Blue Channel Gain Control. Controls the ADC input range
(contrast) of each respective channel. Bigger values give less
contrast.2
0x0A
R/W
7:0
0000 0000
Must be written to 0x00 following a write of Reg. 0x09 for proper
operation.
0x0B
R/W
7:0
0100 0000
Red Offset MSB
8-Bit MSB of the Red Channel Offset Control. Controls the dc offset
(brightness) of each respective channel. Bigger values decrease
brightness.1
0x0C
R/W
7
0*** ****
Red Offset LSB
Linked with Reg. 0x0B to form the 9-bit red offset that controls the
dc offset (brightness) of the red channel in auto-offset mode.
0x0D
R/W
7:0
0100 0000
Green Offset MSB
8-Bit MSB of the Green Channel Offset Control. Controls the dc
offset (brightness) of each respective channel. Bigger values
decrease brightness.1
0x0E
R/W
7
0*** ****
Green Offset LSB
Linked with Reg. 0x0D to form the 9-bit green offset that controls
the dc offset (brightness) of the green channel in auto-offset mode.
0x0F
R/W
7:0
0100 0000
Blue Offset MSB
8-Bit MSB of the Red Channel Offset Control. Controls the dc offset
(brightness) of each respective channel. Bigger values decrease
brightness.1
0x10
R/W
7
0*** ****
Blue Offset LSB
Linked with Reg. 0x0F to form the 9-bit blue offset that controls the
dc offset (brightness) of the blue channel in auto-offset mode.
0x11
R/W
7:0
0010 0000
Sync Separator
Threshold
This register sets the threshold of the sync separator’s digital
comparator.
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相關(guān)代理商/技術(shù)參數(shù) |
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| AD9983AKSTZ-1701 | 制造商:AD 制造商全稱:Analog Devices 功能描述:High Performance 8-Bit Display Interface |
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| AD9983KSTZ-170 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Analog Devices 功能描述: |
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