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參數(shù)資料
| 型號： | AD9981KSTZ-95 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 14/44頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC INTERFACE 10BIT ANALOG 80LQFP |
| 標準包裝： | 1 |
| 應(yīng)用： | 視頻 |
| 接口： | 模擬 |
| 電源電壓： | 3.13 V ~ 3.47 V |
| 封裝/外殼： | 80-LQFP |
| 供應(yīng)商設(shè)備封裝： | 80-LQFP（14x14） |
| 包裝： | 管件 |
| 安裝類型： | 表面貼裝 |
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AD9981
Rev. 0 | Page 21 of 44
DATAIN
P0
P1
P2
P5
P3
P4
P9
P6
P8
P10
P11
P7
HSIN
DATACLK
8 CLOCK CYCLE DELAY
2 CLOCK CYCLE DELAY
DDR NOTES
1. OUTPUT DATACLK MAY BE DELAYED 1/4 CLOCK PERIOD IN THE REGISTERS.
2. SEE PROJECT DOCUMENT FOR VALUES OF F (FALLING EDGE) AND R (RISING EDGE).
3. FOR DDR 4:2:2 MODE: TIMING IS IDENTICAL, VALUES OF F AND R CHANGE.
GENERAL NOTES
1. DATA DELAY MAY VARY ± ONE CLOCK CYCLE, DEPENDING ON PHASE SETTING.
2. ADCs SAMPLE INPUT ON FALLING EDGE OF DATACLK.
3. HSYNC SHOWN IS ACTIVE HIGH (EDGE SHOWN IS LEADING EDGE).
HSOUT
04739-010
F0 R0 F1 R1 F2 R2 F3 R3
Figure 16. DDR Timing Mode
HSYNC TIMING
The Hsync is processed in the AD9981 to eliminate ambiguity
in the timing of the leading edge with respect to the phase-
delayed pixel clock and data.
The Hsync input is used as a reference to generate the pixel
sampling clock. The sampling phase can be adjusted with
respect to Hsync through a full 360° in 32 steps via the phase
adjust register (to optimize the pixel sampling time). Display
systems use Hsync to align memory and display write cycles, so
it is important to have a stable timing relationship between
Hsync output (HSOUT) and the data clock (DATACK).
Three things happen to Hsync in the AD9981. First, the polarity
of Hsync input is determined and thus has a known output pol-
arity. The known output polarity can be programmed either
active high or active low (Register 0x12, Bit 3). Second, HSOUT
is aligned with DATACK and data outputs. Third, the duration
of HSOUT (in pixel clocks) is set via Register 0x13. HSOUT is
the sync signal that should be used to drive the rest of the
display system.
COAST TIMING
In most computer systems, the Hsync signal is provided
continuously on a dedicated wire. In these systems, the Coast
input and function are unnecessary and should not be used.
In some systems, however, Hsync is disturbed during Vsync. In
some cases, Hsync pulses disap-pear. In other systems, such as
those that employ composite sync (Csync) signals or embedded
sync-on-green, Hsync may include equalization pulses or other
distortions during Vsync. To avoid upsetting the clock generator
during Vsync, it is important to ignore these distortions. If the
pixel clock PLL sees extraneous pulses, it attempts to lock to the
new frequency and will have changed frequency by the end of
the Vsync period. It then takes a few lines of correct Hsync
timing to recover at the beginning of a new frame, resulting in a
tearing of the image at the top of the display.
The Coast input is provided to eliminate this problem. It is an
asynchronous input that disables the PLL input and holds the
clock at its current frequency. The PLL can free run for several
lines without significant frequency drift. Coast can be generated
internally by the AD9981 (see Register 0x18) or can be provided
externally by the graphics controller.
When internal Coast is selected (Register 0x18, Bit 7 = 0, and
Register 0x14, Bits [7:6] to select source), Vsync is used as a
basis for determining the position of Coast. The internal Coast
signal is enabled a programmed number of Hsync periods
before the periodic Vsync signal (Precoast Register 0x16) and
dropped a programmed number of Hsync periods after Vsync
(Postcoast Register 0x17). It is recommended that the Vsync
filter be enabled when using the internal Coast function to
allow the AD9981 to determine precisely the number of
Hsyncs/Vsync and their location. In many applications where
disruptions occur and Coast is used, values of 2 for Precoast
and 10 DDR for Postcoast are sufficient to avoid most
extraneous pulses.
OUTPUT FORMATTER
The output formatter is capable of generating several output
formats to be presented to the 30 data output pins. The output
formats and the pin assignments for each format are listed in
Table 11. Also, there are several clock options for the output
clock. The user may select the pixel clock, a 90° phase-shifted
pixel clock, a 2× pixel clock, or a fixed frequency 40 MHz clock
for test purposes. The output clock may also be inverted.
Data output is available as 30 pin RGB or YCbCr or if either
4:2:2 or 4:4:4 DDR is selected, a secondary channel is available.
This secondary channel is always 4:2:2 DDR and allows the
flexibility of having a second channel with the same video data
that can be utilized by another display or a storage device.
Depending on the choice of output modes, the primary output
can be 30 pins, 20 pins or as few as 15 pins.
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相關(guān)代理商/技術(shù)參數(shù) |
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| AD9981XSTZ-110 | 制造商:Analog Devices 功能描述:HIGH PERFORMANCE 10-BIT DISPLAY INTERFACE - Bulk |
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| AD9983A/PCBZ | 功能描述:KIT EVALUATION AD9983A RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:Advantiv® 標準包裝:1 系列:PCI Express® (PCIe) 主要目的:接口，收發(fā)器，PCI Express 嵌入式:- 已用 IC / 零件:DS80PCI800 主要屬性:- 次要屬性:- 已供物品:板 |
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