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參數資料
| 型號： | AD9981KSTZ-95 |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 11/44頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC INTERFACE 10BIT ANALOG 80LQFP |
| 標準包裝： | 1 |
| 應用： | 視頻 |
| 接口： | 模擬 |
| 電源電壓： | 3.13 V ~ 3.47 V |
| 封裝/外殼： | 80-LQFP |
| 供應商設備封裝： | 80-LQFP（14x14） |
| 包裝： | 管件 |
| 安裝類型： | 表面貼裝 |
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AD9981
Rev. 0 | Page 19 of 44
FIELD 1
FIELD 0
SYNC SEPARATOR THRESHOLD
FIELD 1
FIELD 0
23
2
1
4
31
HSYNCIN
VSYNCIN
VSYNCOUT
O/E FIELD
EVEN FIELD
QUADRANT
04739-018
Figure 12. Vsync Filter—Odd/Even
Power Management
To meet display requirements for low standby power, the
AD9981 includes a power-down mode. The power-down state
can be controlled manually (via Pin 17 or Register 0x1E, Bit 3),
or completely automatically by the chip. If automatic control is
selected (0x1E, Bit 4), the AD9981’s decision is based on the
status of the sync detect bits (Register 0x24, Bits 2, 3, 6, and 7). If
either an Hsync or a sync-on-green input is detected on any
input, the chip powers up, or else it powers down. For manual
control, the AD9981 allows flexibility of control through both a
dedicated pin and a register bit. The dedicated pin allows a
hardware watchdog circuit to control power-down, while the
register bit allows power-down to be controlled by software.
With manual power-down control, the polarity of the power-
down pin must be set (0x1E, Bit 2) regardless of whether the pin
is used. If unused, it is recommended to set the polarity to active
high and hardwire the pin to ground with a 10 k resistor.
In power-down mode, there are several circuits that continue to
operate as normal. The serial register and sync detect circuits
maintain power so that the AD9981 can be woken up from
its power-down state. The bandgap circuit maintains power
because it is needed for sync detection. The sync-on-green and
SOGOUT functions continue to operate because the SOGOUT
output is needed when sync detection is performed by a
secondary chip. All of these circuits require minimal power to
operate. Typical standby power on the AD9981 is about 50 mW.
There are two options that can be selected when in power-
down. These are controlled by Bits 0 and 1 in Register 0x1E. The
first bit controls whether the SOGOUT pin is in high impe-
dance or not. In most cases, the user will not place SOGOUT in
high impedance during normal operation. The option to put
SOGOUT in high impedance is included mainly to allow for
factory testing modes. The second option keeps the AD9981
powered up while placing only the outputs in high impedance.
This option is useful when the data outputs from two chips are
connected on a PCB and the user wants to switch
instantaneously between the two.
Table 10. Power-Down Control and Mode Descriptions
Inputs
Mode
Auto Power-Down
Control1
Power-Down2
Sync Detect3
Powered-On or Comments
Power-Up
1
X
1
Everything
Power-Down
1
X
0
Only the serial bus, sync activity detect,
SOG, bandgap reference
Power-Up
0
X
Everything
Power-Down
0
1
X
Only the serial bus, sync activity detect,
SOG, bandgap reference
1 Auto power-down control is set by Register 0x1E, Bit 4.
2 Power-down is controlled by OR’ing Pin 17 with Register 0x1E, Bit 3. The polarity of Pin 17 is set by Register 0x1E, Bit 2.
3 Sync detect is determined by OR’ing Register 0x24, Bits 2, 3, 6, and 7.
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