參數(shù)資料
型號(hào)： AD9981KSTZ-80
廠(chǎng)商： Analog Devices Inc
文件頁(yè)數(shù)： 35/44頁(yè)
文件大?。?/td> 0K
描述： IC INTERFACE 10BIT ANALOG 80LQFP
標(biāo)準(zhǔn)包裝： 90
應(yīng)用： 視頻
接口： 模擬
電源電壓： 3.13 V ~ 3.47 V
封裝/外殼： 80-LQFP
供應(yīng)商設(shè)備封裝： 80-LQFP（14x14）
包裝： 管件
安裝類(lèi)型： 表面貼裝
AD9981
Preliminary Technical Data
Rev. 0 | Page 40 of 44
TWO-WIRE SERIAL CONTROL PORT
A two-wire serial interface control interface is provided. Up to
two AD9981 devices may be connected to the two-wire serial
interface, with each device having a unique address.
The two-wire serial interface comprises a clock (SCL) and a bi-
directional data (SDA) pin. The analog flat panel interface acts
as a slave for receiving and transmitting data over the serial
interface. When the serial interface is not active, the logic levels
on SCL and SDA are pulled high by external pull-up resistors.
Data received or transmitted on the SDA line must be stable for
the duration of the positive-going SCL pulse. Data on SDA must
change only when SCL is low. If SDA changes state while SCL is
high, the serial interface interprets that action as a start or stop
sequence.
The following are the five components to serial bus operation:
Start signal
Slave address byte
Base register address byte
Data byte to read or write
Stop signal
When the serial interface is inactive (SCL and SDA are high),
communications are initiated by sending a start signal. The start
signal is a high-to-low transition on SDA while SCL is high.
This signal alerts all slaved devices that a data transfer sequence
is coming.
The first eight bits of data transferred after a start signal
comprise a 7-bit slave address (the first seven bits) and a single
R/W\ bit (the eighth bit). The R/W\ bit indicates the direction
of data transfer, read from 1 or write to 0 on the slave device. If
the transmitted slave address matches the address of the device
(set by the state of the Serial A0 address [SA0] input pin in
Table 70), the AD9981 acknowledges the match by bringing
SDA low on the 9th SCL pulse. If the addresses do not match,
the AD9981 does not acknowledge it.
Table 70. Serial Port Addresses
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
A6 (MSB)
A5
A4
A3
A2
A1
A0
1
0
1
0
1
0
1
0
1
DATA TRANSFER VIA SERIAL INTERFACE
For each byte of data read or written, the MSB is the first bit in
the sequence.
If the AD9981 does not acknowledge the master device during a
write sequence, the SDA remains high so the master can gener-
ate a stop signal. If the master device does not acknowledge the
AD9981 during a read sequence, the AD9981 interprets this as
end-of-data. The SDA remains high so the master can generate
a stop signal.
Writing data to specific control registers of the AD9981 requires
that the 8-bit address of the control register of interest be writ-
ten after the slave address has been established. This control
register address is the base address for subsequent write opera-
tions. The base address auto-increments by one for each byte of
data written after the data byte intended for the base address. If
more bytes are transferred than there are available addresses,
the address will not increment and remain at its maximum
value of 0x2E. Any base address higher than 0x2E will not pro-
duce an acknowledge signal. Data are read from the control
registers of the AD9981 in a similar manner. Reading requires
two data transfer operations:
The base address must be written with the R/W bit of the slave
address byte low to set up a sequential read operation. Reading
(the R/W\ bit of the slave address byte high) begins at the
previously established base address. The address of the read
register auto-increments after each byte is transferred.
To terminate a read/write sequence to the AD9981, a stop signal
must be sent. A stop signal comprises a low-to-high transition
of SDA while SCL is high.
A repeated start signal occurs when the master device driving
the serial interface generates a start signal without first genera-
ting a stop signal to terminate the current communication. This
is used to change the mode of communication (read, write)
between the slave and master without releasing the serial
interface lines.
SDA
SCL
tBUFF
tSTAH
tDHO
tDSU
tDAL
tDAH
tSTASU
tSTOSU
04739-011
Figure 17. Serial Port Read/Write Timing
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