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| 型號： | AD9981KSTZ-80 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 25/44頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC INTERFACE 10BIT ANALOG 80LQFP |
| 標準包裝： | 90 |
| 應(yīng)用： | 視頻 |
| 接口： | 模擬 |
| 電源電壓： | 3.13 V ~ 3.47 V |
| 封裝/外殼： | 80-LQFP |
| 供應(yīng)商設(shè)備封裝： | 80-LQFP（14x14） |
| 包裝： | 管件 |
| 安裝類型： | 表面貼裝 |
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AD9981
Rev. 0 | Page 31 of 44
0x10
7:5
Blue Channel Offset LSBs
The LSBs of the blue channel offset control combine
with the 8 bits of MSB in the previous register to make
11 bits of offset control.
HSYNC CONTROLS
0x11
7:0
Sync Separator Threshold
This register sets the threshold of the sync separator’s
digital comparator. The value written to this register is
multiplied by 200 ns to get the threshold value.
Therefore, if a value of 5 is written, the digital
comparator threshold is 1 s and any pulses less than 1
S are rejected by the sync separator. There is some
variability to the 200 ns multiplier value. The
maximum variability over all operating conditions is
±20% (160 ns to 240 ns). Since normal Vsync and
Hsync pulse widths differ by a factor of about 500 or
more, the 20% variability is not an issue. The power-
up default value is 32 DDR.
0x12
7
Hsync Source Override
This is the active Hsync override. Setting this to 0
allows the chip to determine the active Hsync source.
Setting it to 1 uses Bit 6 of Register 0x12 to determine
the active Hsync source. Power-up default value is 0.
Table 16.Active Hsync Source Override
Override
Result
0
Hsync Source determined by chip
1
Hsync Source determined by user
Register 0x12, Bit 6
0x12
6
Hsync Source
This bit selects the source of the Hsync for PLL and
sync processing—only if Bit 7 of Register 0x12 is set to
1 or if both syncs are active. Setting this bit to 0
specifies the Hsync from the input pin. Setting it to 1
selects Hsync from SOG. Power-up default is 0.
Table 17. Active Hsync Select Settings
Select
Result
0
Hsync Input
1
Hsync from SOG
0x12
5
Hsync Input Polarity Override
This bit determines whether the chip selects the Hsync
input polarity or if it is specified. Setting this bit to 0
allows the chip to automatically select the polarity of
the input Hsync; setting it to 1 indicates that Bit 4 of
Register 0x12 specifies the polarity. Power-up default
is 0.
Table 18. Hsync Input Polarity Override Settings
Override Bit
Result
0
Hsync Polarity Determined by Chip
1
Hsync Polarity Determined by User
Register 0x12, Bit 4
0x12
4
Input Hsync Polarity
If Bit 5 of Register 0x12 is 1, the value of this bit
specifies the polarity of the input Hsync. Setting this
bit to 0 indicates an active low Hsync; setting this bit
to 1 indicates an active high Hsync. Power-up default
is 1.
Table 19. Hsync Input Polarity Settings
Hsync Polarity Bit
Result
0
Hsync Input Polarity is Negative
1
Hsync Input Polarity is Positive
0x12
3
Hsync Output Polarity
This bit sets the polarity of the Hsync output. Setting
this bit to 0 sets the Hsync output to active low. Setting
this bit to 1 sets the Hsync output to active high.
Power-up default setting is 1.
Table 20. Hsync Output Polarity Settings
Hsync Output
Polarity Bit
Result
0
Hsync Output Polarity is Negative
1
Hsync Output Polarity is Positive
0x13
7:0
Hsync Duration
An 8-bit register that sets the duration of the Hsync
output pulse. The leading edge of the Hsync output is
triggered by the internally-generated, phase-adjusted
PLL feedback clock. The AD9981 then counts a
number of pixel clocks equal to the value in this
register. This triggers the trailing edge of the Hsync
output, which is also phase-adjusted.
VSYNC CONTROLS
0x14
7
Vsync Source Override
This is the active Vsync override. Setting this to 0
allows the chip to determine the active Vsync source,
setting it to 1 uses Bit 6 of Register 0x14 to determine
the active Vsync source. Power-up default value is 0.
Table 21. Active Vsync Source Override
Override
Result
0
Vsync source determined by chip
1
Vsync source determined by user
Register 0x14, Bit 6
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| AD9981KSTZ-95 | 功能描述:IC INTERFACE 10BIT ANALOG 80LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 特色產(chǎn)品:NXP - I2C Interface 標準包裝:1 系列:- 應(yīng)用:2 通道 I²C 多路復用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:825 (CN2011-ZH PDF) 其它名稱:568-1854-1 |
| AD9981XSTZ-110 | 制造商:Analog Devices 功能描述:HIGH PERFORMANCE 10-BIT DISPLAY INTERFACE - Bulk |
| AD9983A | 制造商:AD 制造商全稱:Analog Devices 功能描述:High Performance 8-Bit Display Interface |
| AD9983A/PCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:High Performance 8-Bit Display Interface |
| AD9983A/PCBZ | 功能描述:KIT EVALUATION AD9983A RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:Advantiv® 標準包裝:1 系列:PCI Express® (PCIe) 主要目的:接口，收發(fā)器，PCI Express 嵌入式:- 已用 IC / 零件:DS80PCI800 主要屬性:- 次要屬性:- 已供物品:板 |
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