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| 型號： | AD9981KSTZ-80 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 26/44頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC INTERFACE 10BIT ANALOG 80LQFP |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 應(yīng)用： | 視頻 |
| 接口： | 模擬 |
| 電源電壓： | 3.13 V ~ 3.47 V |
| 封裝/外殼： | 80-LQFP |
| 供應(yīng)商設(shè)備封裝： | 80-LQFP（14x14） |
| 包裝： | 管件 |
| 安裝類型： | 表面貼裝 |
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AD9981
Preliminary Technical Data
Rev. 0 | Page 32 of 44
0x14
6
Vsync Source
This bit selects the source of the Vsync for sync
processing only if Bit 7 of Register 0x14 is set to 1.
Setting Bit 6 to 0 specifies the Vsync from the input
pin; setting it to 1 selects Vsync from the sync
separator. Power-up default is 0.
Table 22. Active Vsync Select Settings
Select
Result
0
Vsync input
1
Vsync from sync separator
0x14
5
Vsync Input Polarity Override
This bit sets whether the chip selects the Vsync input
polarity or if it is specified. Setting this bit to 0 allows
the chip to automatically select the polarity of the
input Vsync. Setting this bit to 1 indicates that Bit 4 of
Register 0x14 specifies the polarity. Power-up default
is 0.
Table 23. Vsync Input Polarity Override Settings
Override Bit
Result
0
Vsync polarity determined by chip
1
Vsync polarity determined by user
Register 0x14, Bit 4
0x14
4
Input Vsync Polarity
If Bit 5 of Register 0x14 is 1, the value of this bit
specifies the polarity of the input Vsync. Setting this
bit to 0 indicates an active low Vsync; setting this bit to
1 indicates an active high Vsync. Power-up default is 1.
Table 24. Vsync Input Polarity Settings
Override Bit
Result
0
Vsync input polarity is negative
1
Vsync input polarity is positive
0x14
3
Vsync Output Polarity
This bit sets the polarity of the Hsync output. Setting
this bit to 0 sets the Hsync output to active low. Setting
this bit to 1 sets the Hsync output to active high.
Power-up default is 1.
Table 25. Vsync Output Polarity Settings
Vsync Output
Polarity Bit
Result
0
Vsync output polarity is negative
1
Vsync output polarity is positive
0x14
2
Vsync Filter Enable
This bit enables the Vsync filter allowing precise
placement of the Vsync with respect to the Hsync
and facilitating the correct operation of the Hsyncs/
Vsync count.
Table 26. Vsync Filter Enable
Vsync Filter Bit
Result
0
Vsync filter disabled
1
Vsync filter enabled
0x14
1
Vsync Duration Enable
This enables the Vsync duration block, which is
designed to be used with the Vsync filter. Setting the
bit to 0 leaves the Vsync output duration unchanged.
Setting the bit to 1 sets the Vsync output duration
based on Register 0x15. Power-up duration is 0.
Table 27. Vsync Duration Enable
Vsync Duration Bit
Result
0
Vsync output duration is unchanged
1
Vsync output duration is set by Register
0x15
0x15
7:0
Vsync Duration
This is used to set the output duration of the Vsync,
and is designed to be used with the Vsync filter. This is
valid only if Register 0x14, Bit 1 is set to 1. Power-up
default is 10 DDR.
COAST AND CLAMP CONTROLS
0x16
7:0
Precoast
This register allows the internally generated Coast
signal to be applied prior to the Vsync signal. This is
necessary in cases where pre-equalization pulses are
present. The step size for this control is one Hsync
period. For Precoast to work correctly, it is necessary
for the Vsync filter (0x14, Bit 2) and sync processing
filter (Register 0x20, Bit 1) both to be either enabled or
disabled. The power-up default is 00.
0x17
7:0
Postcoast
This register allows the internally generated Coast
signal to be applied following the Vsync signal. This is
necessary in cases where postequalization pulses are
present. The step size for this control is one Hsync
period. For Postcoast to work correctly, it is necessary
for the Vsync filter (0x14, Bit 2) and sync processing
filter (0x20, Bit 1) both to be either enabled or
disabled. The power-up default is 00.
0x18
7
Coast Source
This bit is used to select the active Coast source. The
choices are the COAST input pin or vsync. If Vsync is
selected, the additional decision of using the VSYNC
input pin or the output from the sync separator needs
to be made (Register 0x14, Bits [7: 6]).
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| AD9981KSTZ-95 | 功能描述:IC INTERFACE 10BIT ANALOG 80LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 特色產(chǎn)品:NXP - I2C Interface 標(biāo)準(zhǔn)包裝:1 系列:- 應(yīng)用:2 通道 I²C 多路復(fù)用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:825 (CN2011-ZH PDF) 其它名稱:568-1854-1 |
| AD9981XSTZ-110 | 制造商:Analog Devices 功能描述:HIGH PERFORMANCE 10-BIT DISPLAY INTERFACE - Bulk |
| AD9983A | 制造商:AD 制造商全稱:Analog Devices 功能描述:High Performance 8-Bit Display Interface |
| AD9983A/PCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:High Performance 8-Bit Display Interface |
| AD9983A/PCBZ | 功能描述:KIT EVALUATION AD9983A RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:Advantiv® 標(biāo)準(zhǔn)包裝:1 系列:PCI Express® (PCIe) 主要目的:接口，收發(fā)器，PCI Express 嵌入式:- 已用 IC / 零件:DS80PCI800 主要屬性:- 次要屬性:- 已供物品:板 |
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