參數(shù)資料
型號： AD9974BBCZ
廠商： Analog Devices Inc
文件頁數(shù)： 7/52頁
文件大?。?/td> 0K
描述： IC CCDSP DUAL 14BIT 100-CSPBGA
標準包裝： 1
類型： CCD 信號處理器，14 位
輸入類型： 邏輯
輸出類型： 邏輯
接口： 3 線串口
電流 - 電源： 55mA
安裝類型： 表面貼裝
封裝/外殼： 100-LFBGA，CSPBGA
供應商設(shè)備封裝： 100-CSBGA（9x9）
包裝： 托盤
AD9974
Rev. A | Page 15 of 52
PROGRAMMABLE TIMING GENERATION
PRECISION TIMING HIGH SPEED TIMING CORE
The AD9974 generates flexible high speed timing signals using
the Precision Timing core. This core, composed of the Reset
Gate RG, Horizontal Driver H1 to Horizontal Driver H4, and
SHP/SHD sample clocks, is the foundation for generating the
timing for both the CCD and the AFE. A unique architecture
makes it routine for the system designer to optimize image
quality by providing precise control over the horizontal CCD
readout and the AFE correlated double sampling.
Timing Resolution
The Precision Timing core uses a master clock input (CLI_X)
as a reference. This clock input should be the same as the CCD
pixel clock frequency. Figure 17 illustrates how the internal timing
core divides the master clock period into 64 steps or edge positions;
therefore, the edge resolution of the Precision Timing core is
(tCLI/64). For more information on using the CLI input, refer to
Using a 65 MHz CLI frequency, the edge resolution of the
Precision Timing core is approximately 240 ps. If a 1× system
clock is not available, it is possible to use a 2× reference clock
by programming the CLIDIVIDE register (Address 0x0D). The
AD9974 then internally divides the CLI frequency by 2.
High Speed Clock Programmability
Figure 18 shows when the high speed clocks, RG, H1 to H4,
SHP, and SHD, are generated. The RG pulse has programmable
rising and falling edges and can be inverted using the polarity
control. The H1 and H2 horizontal clocks have separate program-
mable rising and falling edges, as well as separate polarity control.
The AD9974 provides additional HCLK-mode programmability,
as described in Table 9.
The edge location registers are each six bits wide, allowing the
selection of all 64 edge locations. Figure 21 shows the default
timing locations for all of the high speed clock signals.
P[0]
P[64] = P[0]
P[16]
P[32]
P[48]
1 PIXEL
PERIOD
CLI
tCLIDLY
POSITION
NOTES
1. THE PIXEL CLOCK PERIOD IS DIVIDED INTO 64 POSITIONS, PROVIDING FINE EDGE RESOLUTION FOR HIGH SPEED CLOCKS.
2. THERE IS A FIXED DELAY FROM THE CLI INPUT TO THE INTERNAL PIXEL PERIOD POSITION (
tCLIDLY).
0
5
955
-01
7
Figure 17. High Speed Clock Resolution from CLI Master Clock Input
CCD
SIGNAL
RG
PROGRAMMABLE CLOCK POSITIONS:
1SHP SAMPLE LOCATION.
2SHD SAMPLE LOCATION.
3RG RISING EDGE.
4RG FALLING EDGE.
5H1 RISING EDGE.
6H1 FALLING EDGE.
1
2
34
H2, H4
H1, H3
56
05
95
5-
0
18
Figure 18. High Speed Clock Programmable Locations (HCLK Mode 1)
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