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| 型號： | AD9974BBCZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 42/52頁 |
| 文件大小： | 0K |
| 描述： | IC CCDSP DUAL 14BIT 100-CSPBGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | CCD 信號處理器，14 位 |
| 輸入類型： | 邏輯 |
| 輸出類型： | 邏輯 |
| 接口： | 3 線串口 |
| 電流 - 電源： | 55mA |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LFBGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 100-CSBGA（9x9） |
| 包裝： | 托盤 |
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AD9974
Rev. A | Page 47 of 52
Table 29. Update Control Registers
Address
Data Bit
Content
Default
Value
Update
Name
Description
0x60
[15:0]
1803
SCK
AFE_UPDT_SCK
Enable SCK update of AFE registers. Each bit corresponds to one
address location.
AFE_UPDT_SCK[0] = 1, update Address 0x00 on SL rising edge.
AFE_UPDT_SCK[1] = 1, update Address 0x01 on SL rising edge.
…
AFE_UPDT_SCK[15] = 1, update Address 0x0F on SL rising edge.
[27:16]
Unused
Set unused register = 0 if accessed.
0x61
[15:0]
E7FC
SCK
AFE_UPDT_VD
Enable VD update of AFE registers. Each bit corresponds to one
address location.
AFE_UPDT_VD[0] = 1, update Address 0x00 on VD rising edge.
AFE_UPDT_VD[1] = 1, update Address 0x01 on VD rising edge.
…
AFE_UPDT_VD[15] = 1, update Address 0x0F on VD rising edge.
[27:16]
Unused
Set unused register to 0 if accessed.
0x62
[15:0]
F8FD
SCK
MISC_UPDT_SCK
Enable SCK update of miscellaneous registers. Address 0x10 to
Address 0x1F.
[27:16]
Unused
Set unused register to 0 if accessed.
0x63
[15:0]
0702
SCK
MISC_UPDT_VD
Enable VD update of miscellaneous registers, Address 0x10 to
Address 0x1F.
[27:16]
Unused
Set unused register to 0 if accessed.
0x64
[15:0]
FFF9
SCK
VDHD_UPDT_SCK
Enable SCK update of VDHD Registers, Address 0x20 to Address 0x22.
[27:16]
Unused
Set unused register to 0 if accessed.
0x65
[15:0]
0006
SCK
VDHD_UPDT_VD
Enable VD update of VDHD registers, Address 0x20 to Address 0x22.
[27:16]
Unused
Set unused register to 0 if accessed.
0x66
[15:0]
FFFF
SCK
TGCORE_UPDT_SCK
Enable SCK update of timing core registers, Address 0x30 to
Address 0x37.
[27:16]
Unused
Set unused register to 0 if accessed.
0x67
[15:0]
0000
SCK
TGCORE_UPDT_VD
Enable VD update of timing core registers, Address 0x30 to
Address 0x37.
[27:16]
Unused
Set unused register to 0 if accessed.
0x68 to
0x72
[27:0]
SCK
Unused
Set unused register to 0 if accessed.
Table 30. HPAT Registers (HPAT Registers Always Start at Address 0x800)
Address
Data Bit
Content
Default
Value
Update
Name
Description
0x00
[12:0]
X
SCP
HBLKTOGO1
First HBLK Toggle Position for Odd Lines, or RA0H1REPA/B/C.
[25:13]
X
HBLKTOGO2
Second HBLK Toggle Position for Odd Lines, or RA1H1REPA/B/C.
[27:26]
X
Unused
Set unused bits to 0.
0x01
[12:0]
X
SCP
HBLKTOGO3
Third HBLK Toggle Position for Odd Lines, or RA2H1REPA/B/C.
[25:13]
X
HBLKTOGO4
Fourth HBLK Toggle Position for Odd Lines, or RA3H1REPA/B/C.
[27:26]
X
Unused
Set unused bits to 0.
0x02
[12:0]
X
SCP
HBLKTOGO5
Fifth HBLK Toggle Position for Odd Lines, or RA4H1REPA/B/C.
[25:13]
X
HBLKTOGO6
Sixth HBLK Toggle Position for Odd Lines, or RA5H1REPA/B/C.
[27:26]
X
Unused
Set unused bits to 0.
0x03
[12:0]
X
SCP
HBLKTOGE1
First HBLK Toggle Position for Even Lines, or RA0H2REPA/B/C.
[25:13]
X
HBLKTOGE2
Second HBLK Toggle Position for Even Lines, or RA1H2REPA/B/C.
[27:26]
X
Unused
Set unused bits to 0.
0x04
[12:0]
X
SCP
HBLKTOGE3
Third HBLK Toggle Position for Even Lines, or RA2H2REPA/B/C.
[25:13]
X
HBLKTOGE4
Fourth HBLK Toggle Position for Even Lines, or RA3H2REPA/B/C.
[27:26]
X
Unused
Set unused bits to 0.
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|---|---|
| AD9974BBCZRL | 功能描述:IC CCDSP DUAL 14BIT 100-CSPBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 傳感器和探測器接口 系列:- 其它有關(guān)文件:Automotive Product Guide 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:74 系列:- 類型:觸控式傳感器 輸入類型:數(shù)字 輸出類型:數(shù)字 接口:JTAG，串行 電流 - 電源:100µA 安裝類型:表面貼裝 封裝/外殼:20-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:20-TSSOP 包裝:管件 |
| AD9975 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Broadband Modem Mixed-Signal Front End |
| AD9975ABST | 制造商:AD 制造商全稱:Analog Devices 功能描述:Broadband Modem Mixed-Signal Front End |
| AD9975ABSTEB | 制造商:AD 制造商全稱:Analog Devices 功能描述:Broadband Modem Mixed-Signal Front End |
| AD9975ABSTRL | 制造商:AD 制造商全稱:Analog Devices 功能描述:Broadband Modem Mixed-Signal Front End |
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