AVDD and DVDD = 1.8 V ± 5%; DVDD_I/O = 3.3 V ± 5%; T = 25°C; R
參數(shù)資料
型號(hào)： AD9958BCPZ-REEL7
廠商： Analog Devices Inc
文件頁數(shù)： 34/44頁
文件大?。?/td> 0K
描述： IC DDS DUAL 10BIT DAC 56LFCSP
產(chǎn)品培訓(xùn)模塊： Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
設(shè)計(jì)資源： Low Jitter Sampling Clock Generator for High Performance ADCs Using AD9958/9858 and AD9515 (CN0109)
Phase Coherent FSK Modulator (CN0186)
標(biāo)準(zhǔn)包裝： 750
分辨率（位）： 10 b
主 fclk： 500MHz
調(diào)節(jié)字寬（位）： 32 b
電源電壓： 1.71 V ~ 1.96 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 56-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 56-LFCSP-VQ（8x8）
包裝： 帶卷 (TR)
配用： AD9958/PCBZ-ND - BOARD EVALUATION FOR AD9958
AD9958
Data Sheet
Rev. B | Page 4 of 44
SPECIFICATIONS
AVDD and DVDD = 1.8 V ± 5%; DVDD_I/O = 3.3 V ± 5%; T = 25°C; RSET = 1.91 k; external reference clock frequency = 500 MSPS
(REFCLK multiplier bypassed), unless otherwise noted.
Table 1.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
REFERENCE CLOCK INPUT CHARACTERISTICS
Frequency Range
REFCLK Multiplier Bypassed
1
500
MHz
REFCLK Multiplier Enabled
10
125
MHz
Internal VCO Output Frequency Range
VCO Gain Control Bit Set High1
255
500
MHz
VCO Gain Control Bit Set Low1
100
160
MHz
Crystal REFCLK Source Range
20
30
MHz
Input Level
200
1000
mV
Measured at each pin (single-ended)
Input Voltage Bias Level
1.15
V
Input Capacitance
2
pF
Input Impedance
1500
Duty Cycle with REFCLK Multiplier Bypassed
45
55
%
Duty Cycle with REFCLK Multiplier Enabled
35
65
%
CLK Mode Select (Pin 24) Logic 1 Voltage
1.25
1.8
V
1.8 V digital input logic
CLK Mode Select (Pin 24) Logic 0 Voltage
0.5
V
1.8 V digital input logic
DAC OUTPUT CHARACTERISTICS
Must be referenced to AVDD
Resolution
10
Bits
Full-Scale Output Current
1.25
10
mA
Gain Error
10
+10
% FS
Channel-to-Channel Output Amplitude Matching Error
2.5
+2.5
%
Output Current Offset
1
25
A
Differential Nonlinearity
±0.5
LSB
Integral Nonlinearity
±1.0
LSB
Output Capacitance
3
pF
Voltage Compliance Range
AVDD
0.50
AVDD +
0.50
V
Channel-to-Channel Isolation
72
dB
DAC supplies tied together (see
WIDEBAND SFDR
The frequency range for wideband SFDR
is defined as dc to Nyquist
1 MHz to 20 MHz Analog Output
65
dBc
20 MHz to 60 MHz Analog Output
62
dBc
60 MHz to 100 MHz Analog Output
59
dBc
100 MHz to 150 MHz Analog Output
56
dBc
150 MHz to 200 MHz Analog Output
53
dBc
NARROW-BAND SFDR
1.1 MHz Analog Output (±10 kHz)
90
dBc
1.1 MHz Analog Output (±50 kHz)
88
dBc
1.1 MHz Analog Output (±250 kHz)
86
dBc
1.1 MHz Analog Output (±1 MHz)
85
dBc
15.1 MHz Analog Output (±10 kHz)
90
dBc
15.1 MHz Analog Output (±50 kHz)
87
dBc
15.1 MHz Analog Output (±250 kHz)
85
dBc
15.1 MHz Analog Output (±1 MHz)
83
dBc
40.1 MHz Analog Output (±10 kHz)
90
dBc
40.1 MHz Analog Output (±50 kHz)
87
dBc
40.1 MHz Analog Output (±250 kHz)
84
dBc
40.1 MHz Analog Output (±1 MHz)
82
dBc
75.1 MHz Analog Output (±10 kHz)
87
dBc
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