- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1894 > AD9958BCPZ-REEL7 (Analog Devices Inc)IC DDS DUAL 10BIT DAC 56LFCSP PDF資料下載
參數(shù)資料
| 型號： | AD9958BCPZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 15/44頁 |
| 文件大小： | 0K |
| 描述： | IC DDS DUAL 10BIT DAC 56LFCSP |
| 產(chǎn)品培訓模塊： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 設計資源： | Low Jitter Sampling Clock Generator for High Performance ADCs Using AD9958/9858 and AD9515 (CN0109) Phase Coherent FSK Modulator (CN0186) |
| 標準包裝： | 750 |
| 分辨率（位）： | 10 b |
| 主 fclk： | 500MHz |
| 調(diào)節(jié)字寬（位）： | 32 b |
| 電源電壓： | 1.71 V ~ 1.96 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 56-LFCSP-VQ（8x8） |
| 包裝： | 帶卷 (TR) |
| 配用： | AD9958/PCBZ-ND - BOARD EVALUATION FOR AD9958 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁當前第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁
AD9958
Data Sheet
Rev. B | Page 22 of 44
In modulation mode, the amplitude frequency phase (AFP)
select bits (CFR[23:22]) and modulation level bits (FR1[9:8])
are programmed to configure the modulation type and level
(see Table 6 and Table 7). Note that the linear sweep enable bit
must be set to Logic 0 in direct modulation mode.
Table 6. Modulation Type Configuration
AFP Select
(CFR[23:22])
Linear Sweep Enable
(CFR[14])
Description
00
X
Modulation disabled
01
0
Amplitude modulation
10
0
Frequency modulation
11
0
Phase modulation
Table 7. Modulation Level Selection
Modulation Level (FR1[9:8])
Description
00
Two-level modulation
01
Four-level modulation
10
Eight-level modulation
11
16-level modulation
When modulating, the RU/RD function can be limited based
on pins available for controlling the feature. The SDIO_x pins
are for RU/RD only, not for modulation.
Table 8. RU/RD Profile Pin Assignments
Ramp-Up/Ramp-Down
(RU/RD) (FR1[11:10])
Description
00
RU/RD disabled
01
Only Profile Pin P2 and Profile Pin P3
available for RU/RD operation
10
Only Profile Pin P3 available for RU/RD
operation
11
Only SDIO_1, SDIO_2, and SDIO_3
pins available for RU/RD operation;
this forces the serial I/O to be used
only in 1-bit mode
If the profile pins are used for RU/RD, Logic 0 is for ramp-up
and Logic 1 is for ramp-down.
Because of the two channels and limited data pins, it is
necessary to assign the profile pins and/or SDIO_1, SDIO_2,
and SDIO_3 pins to a dedicated channel. This is controlled by
the profile pin configuration (PPC) bits (FR1[14:12]). Each of the
following modulation descriptions incorporates data pin
assignments.
Two-Level Modulation—No RU/RD
The modulation level bits (FR1[9:8]) are set to 00 (two-level).
The AFP select bits (CFR[23:22]) are set to the desired modulation
type. The RU/RD bits (FR1[11:10]) and the linear sweep enable
bit (CFR[14]) are disabled. Table 9 displays how the profile pins
and channels are assigned.
As shown in Table 9, only Profile Pin P2 can be used to modulate
Channel 0. If frequency modulation is selected and Profile Pin P2
is Logic 0, Channel Frequency Tuning Word 0 (Register 0x04) is
chosen; if Profile Pin P2 is Logic 1, Channel Word 1 (Register
0x0A) is chosen.
Four-Level Modulation—No RU/RD
The modulation level bits are set to 01 (four-level). The AFP
select bits (CFR[23:22]) are set to the desired modulation type.
The RU/RD bits (FR1[11:10]) and the linear sweep enable bit
(CFR[14]) are disabled. Table 10 displays how the profile pins
and channels are assigned to each other.
For the conditions in Table 10, the profile (channel word)
register chosen is based on the 2-bit value presented to Profile
Pins [P0:P1] or Profile Pins [P2:P3].
For example, if PPC = 101, [P0:P1] = 11, and [P2:P3] = 01, then
the contents of the Channel Word 3 register of Channel 0 are
presented to the output of Channel 0 and the contents of the
Channel Word 1 register of Channel 1 are presented to the
output of Channel 1.
Table 9. Profile Pin Channel Assignments
Profile Pin Configuration (PPC) (FR1[14:12])
P0
P1
P2
P3
Description
XXX
N/A
CH0
CH1
Two-level modulation, both channels, no RU/RD
Table 10. Profile Pin and Channel Assignments
Profile Pin Configuration (PPC) (FR1[14:12])
P0
P1
P2
P3
Description
101
CH0
CH1
Four-level modulation on CH0 and CH1, no RU/RD
相關PDF資料 |
PDF描述 |
|---|---|
| AD9959BCPZ-REEL7 | IC DDS QUAD 10BIT DAC 56LFCSP |
| AD9970BCPZRL7 | IC PROCESSOR CCD SIGNAL 32-LFCSP |
| AD9972BBCZRL | IC CCD SGNL PROC 14BIT 100CSPBGA |
| AD9973BBCZ | IC CCD SGNL PROC 14BIT 84-CSPBGA |
| AD9974BBCZRL | IC CCDSP DUAL 14BIT 100-CSPBGA |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD9959 | 制造商:AD 制造商全稱:Analog Devices 功能描述:4 Channel 500MSPS DDS with 10-bit DACs |
| AD9959/PCBZ | 功能描述:BOARD EVALUATION FOR AD9959 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標準包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源 |
| AD9959/PCBZ | 制造商:Analog Devices 功能描述:AD9959, DDS, DAC, GUI, USB, EVALUATION B |
| AD9959/PCBZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:4-Channel, 500 MSPS DDS with 10-Bit DACs |
| AD9959_08 | 制造商:AD 制造商全稱:Analog Devices 功能描述:4-Channel, 500 MSPS DDS with 10-Bit DACs |
發(fā)布緊急采購，3分鐘左右您將得到回復。