參數(shù)資料
型號(hào)： AD9958BCPZ-REEL7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 33/44頁(yè)
文件大?。?/td> 0K
描述： IC DDS DUAL 10BIT DAC 56LFCSP
產(chǎn)品培訓(xùn)模塊： Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
設(shè)計(jì)資源： Low Jitter Sampling Clock Generator for High Performance ADCs Using AD9958/9858 and AD9515 (CN0109)
Phase Coherent FSK Modulator (CN0186)
標(biāo)準(zhǔn)包裝： 750
分辨率（位）： 10 b
主 fclk： 500MHz
調(diào)節(jié)字寬（位）： 32 b
電源電壓： 1.71 V ~ 1.96 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 56-VFQFN 裸露焊盤(pán)，CSP
供應(yīng)商設(shè)備封裝： 56-LFCSP-VQ（8x8）
包裝： 帶卷 (TR)
配用： AD9958/PCBZ-ND - BOARD EVALUATION FOR AD9958
Data Sheet
AD9958
Rev. B | Page 39 of 44
DESCRIPTIONS FOR CONTROL REGISTERS
Channel Select Register (CSR)—Address 0x00
One byte is assigned to this register.
The CSR determines if channels are enabled or disabled by the status of the two channel enable bits. Both channels are enabled by their
default state. The CSR also determines which serial mode of operation is selected. In addition, the CSR offers a choice of MSB first or LSB
first format.
Table 31. Bit Descriptions for CSR
Bit
Mnemonic
Description
7:6
Channel [1:0] enable
Bits are active immediately after being written. They do not require an I/O update to take effect.
There are two sets of channel registers and profile (channel word) registers, one per channel. This
is not shown in the channel register map or the profile register map. The addresses of all channel
registers and profile registers are the same for each channel. Therefore, the channel enable bits
distinguish the channel registers and profile registers values of each channel. For example,
10 = only Channel 1 receives commands from the channel registers and profile registers.
01 = only Channel 0 receives commands from the channel registers and profile registers.
11 = both Channel 0 and Channel 1 receive commands from the channel registers and profile
registers.
5:4
Open
3
Must be 0
Must be set to 0.
2:1
Serial I/O mode select
00 = single-bit serial (2-wire mode).
01 = single-bit serial (3-wire mode).
10 = 2-bit serial mode.
11 = 4-bit serial mode.
See the Serial I/O Modes of Operation section for more details.
0
LSB first
0 = the serial interface accepts serial data in MSB first format (default).
1 = the serial interface accepts serial data in LSB first format.
Function Register 1 (FR1)—Address 0x01
Three bytes are assigned to this register. FR1 is used to control the mode of operation of the chip.
Table 32. Bit Descriptions for FR1
Bit
Mnemonic
Description
23
VCO gain control
0 = the low range (system clock below 160 MHz) (default).
1 = the high range (system clock above 255 MHz).
22:18
PLL divider ratio
If the value is 4 or 20 (decimal) or between 4 and 20, the PLL is enabled and the value sets the
multiplication factor. If the value is outside of 4 and 20 (decimal), the PLL is disabled.
17:16
Charge pump control
00 (default) = the charge pump current is 75 A.
01 = charge pump current is 100 A.
10 = charge pump current is 125 A.
11 = charge pump current is 150 A.
15
Open
14:12
Profile pin configuration (PPC)
The profile pin configuration bits control the configuration of the data and SDIO_x pins for the
different modulation modes. See the Modulation Mode section in this document for details.
11:10
Ramp-up/ramp-down (RU/RD)
The RU/RD bits control the amplitude ramp-up/ramp-down time of a channel. See the Output
Amplitude Control Mode section for more details.
9:8
Modulation level
The modulation (FSK, PSK, and ASK) level bits control the level (2/4/8/16) of modulation to be
performed for a channel. See the Modulation Mode section for more details.
7
Reference clock input
0 = the clock input circuitry is enabled for operation (default).
power-down
1 = the clock input circuitry is disabled and is in a low power dissipation state.
相關(guān)PDF資料
PDF描述
AD9959BCPZ-REEL7 IC DDS QUAD 10BIT DAC 56LFCSP
AD9970BCPZRL7 IC PROCESSOR CCD SIGNAL 32-LFCSP
AD9972BBCZRL IC CCD SGNL PROC 14BIT 100CSPBGA
AD9973BBCZ IC CCD SGNL PROC 14BIT 84-CSPBGA
AD9974BBCZRL IC CCDSP DUAL 14BIT 100-CSPBGA
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9959 制造商:AD 制造商全稱:Analog Devices 功能描述:4 Channel 500MSPS DDS with 10-bit DACs
AD9959/PCBZ 功能描述:BOARD EVALUATION FOR AD9959 RoHS:是 類別:編程器，開(kāi)發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源
AD9959/PCBZ 制造商:Analog Devices 功能描述:AD9959, DDS, DAC, GUI, USB, EVALUATION B
AD9959/PCBZ1 制造商:AD 制造商全稱:Analog Devices 功能描述:4-Channel, 500 MSPS DDS with 10-Bit DACs
AD9959_08 制造商:AD 制造商全稱:Analog Devices 功能描述:4-Channel, 500 MSPS DDS with 10-Bit DACs
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*