參數(shù)資料
型號： AD9957BSVZREEL13
廠商： ANALOG DEVICES INC
元件分類： 通信及網(wǎng)絡
英文描述： 1 GSPS Quadrature Digital Upconverter w/18-Bit IQ Data Path and 14-Bit DAC
中文描述： SPECIALTY TELECOM CIRCUIT, QFP48
封裝： PLASTIC, MS-026-AED-HD, TQFP-48
文件頁數(shù)： 17/38頁
文件大?。?/td> 602K
代理商： AD9957BSVZREEL13
PRELIMINARY TECHNICAL DATA
AD9957
Rev. PrF | Page 17 of 38
The timing relationship between TxENABLE, PDCLK, and
DATA is shown in Figure 12.
t
DH
I
0
TxENABLE
PDCLK
D<13:0>
I
K
I
K – 1
I
3
I
2
I
1
0
t
DH
t
DS
t
DS
Figure 12. 18-Bit Parallel Port Timing Diagram—Interpolating DAC Mode
SINGLE-TONE MODE
DDS
cos(
ω
t+
θ
)
sin(
ω
t+
θ
)
DAC
(14-b)
θ
Halfband
Filters
(4x)
18
Parallel Data
Timing &
Control
I/Q In
Internal Clock Timing & Control
PDClk
Clock
Multiplier
RefClk
S
P
RefClk
Halfband
Filters
(4x)
Inv.
CCI
Inv.
CCI
DAC
Rset
Iout
Iout
0
1
0
1
D
R
0
1
AD9957: Single-Tone Mode
0
3
2
1
0
1
x
sin(x)
TxEn
I
Q
ω
2
0
1
2
C
AUX
DAC
(8-b)
8
DAC
Gain
Serial I/O
Port
S
S
Programming
Registers
2
S
P
3
R
RAM
Power
Down
Control
P
D
C
I Q
C
S
θ
F
S
2
G
O
2
FTW
CCI
(1x -63x)
CCI
(1x - 63x)
θ
0
1
Freq.
Ramp
Logic
PW
F
0
1
R
R
I
Q
S
Figure 13: Single-Tone Mode
A block diagram of the AD9957 operating in the single-tone
mode is shown in Figure 13; grayed out items are inactive. In
this mode, both I and Q data paths are disabled from the 18-bit
parallel data port up to and including the modulator. The in-
ternal DDS core produces a signal whose frequency depends on
the programmed tuning word. The user may select either the
cosine (default) or sine output of the DDS. The sinusoid at the
DDS output can be scaled via a 14-bit amplitude scale factor
(ASF) and optionally routed through the Inverse SINC filter.
Amplitude Scale Factor (ASF)
Output amplitude is controlled by a 14-bit digital multiplier
called the Amplitude Scale Factor (ASF), which is programmed
via the appropriate control registers. It is available for each of
the eight profiles. The LSB weight is 2
–14
, which yields a multi-
plier range of 0 to 1.99993896484375 (1-2
-14
).
In addition to the ability to generate single tone signals in this
mode, the AD9957 can also provide 2-, 4-, or 8-level modula-
tion of frequency, phase, or amplitude by means of the eight
available profile registers and the Profile<0:2> pins
.
I/O_UPDATE Pin
In the single-tone mode, the I/O_UPDATE pin serves as a sig-
nal update strobe. Frequency, phase and amplitude control
words for the DDS are programmed via the serial port (see the
Control Register description). The serial port is an asynchro-
nous interface; the I/O_UPDATE pin allows for synchroniza-
tion of the AD9957 output with external circuitry when new
frequency, phase, or amplitude values are programmed into the
on-chip profile registers. A rising edge initiates transfer of the
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