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參數(shù)資料
| 型號： | AD9957BSVZREEL13 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | 1 GSPS Quadrature Digital Upconverter w/18-Bit IQ Data Path and 14-Bit DAC |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, QFP48 |
| 封裝： | PLASTIC, MS-026-AED-HD, TQFP-48 |
| 文件頁數(shù)： | 11/38頁 |
| 文件大小： | 602K |
| 代理商： | AD9957BSVZREEL13 |
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PRELIMINARY TECHNICAL DATA
AD9957
Rev. PrF | Page 11 of 38
DDS
cos( t+ )
sin( t+ )
DAC
(14-b)
FTW
CCI
(1x -63x)
C
I
C
(1x - 63x)
Halfband
Filters
(4x)
Internal Clock Timing & Control
PDClk
SerialI/O
Port
S
S
Programming
Registers
2
S
P
3
R
Clock
Multiplier
RefClk
S
P
RefClk
RAM
Halfband
Filters
(4x)
Inv.
CCI
Inv.
CCI
Power
Down
Control
P
D
DAC
Rset
Iout
Iout
0
1
0
1
F
O
R
M
A
T
T
E
R
C
R
0
1
I Q
C
0
3
2
1
0
1
x
sin(x)
S
TxEn
AUX
DAC
(8-b)
I
Q
2
0
1
2
C
PW
8
DAC
Gain
2
S
2
O
IS
QS
IS
QS
FTW
PW OSF
OSF
I In
Q In
Halfband
Filters
(4x)
Halfband
Filters
(4x)
Serial Data
Timing and
Control
Fixed
Interpolators
Programmable
Interpolators
Quadrature
Modulator
Inverse Sinc
Filter
Figure 4: Quadrature Modulation Mode -- BlackFin Interface
SIGNAL PROCESSING (QDUC & BFI MODES)
To better understand the operation of the AD9957 it is helpful
to follow the signal path in quadrature modulation mode from
the parallel data port to the output of the DAC, examining the
function of each block (refer to Figure 4).
All timing within the AD9957 is provided by the internal sys-
tem clock (SYSCLK) signal, which is generated from the timing
source provided to the REFCLK pins.
PDCLK Pin
The timing of input data supplied to the AD9957 is easily facili-
tated with the PDCLK output pin, which serves as a data clock
timing source. In QDUC mode, PDCLK controls the timing of
the 18-bit parallel input port. In BFI mode, PDCLK controls
the timing of the dual serial input port. The PDCLK is provided
as a continuous clock (i.e., always active). However, even
though the PDCLK output is active by default, it can be disabled
via the
Enable PDCLK
bit in the register map.
In QDUC mode, the AD9957 expects alternating I and Q data
words at the parallel port (see Figure 5). Each rising edge of
PDCLK captures one 16-bit word; that is, two PDCLK cycles
per I/Q pair.. In BFI mode, the AD9957 expects two serial bit
streams each segmented into 16-bit words with each rising edge
of PDCLK indicating a new bit. In either case, the output clock
rate is f
DATA
as explained in the
Input Data Assembler
section.
TxEnable Pin
The rising edge of the TxENABLE signal is used to synchronize
the device. While TxENABLE is in the Logic 0 state, the device
ignores the data applied to the parallel port allowing the inter-
nal data path to be flushed by forcing zeros down the I and Q
data pathways. On the rising edge of TxENABLE, the device is
ready for the first I word. The first I word is latched into the
device coincident with the rising edge of PDCLK. The next
rising edge of PDCLK latches in a Q word, etc., until
TxENABLE is set to a Logic 0 state by the user.
It is important that the user ensure an even number of PDCLK
intervals are observed during any given TxENABLE period. The
device must capture
both
an I and a Q sample before the data is
processed along the signal chain.
In BFI mode, operation of the TxENABLE pin is similar except
that instead of the rising edge marking the first "I word", it
marks the first I (and Q) bit in a serial frame.
It is important that the user ensure a multiple of 16 PDCLK
cycles are observed during any given TxENABLE period. The
device must capture a full 16-bit I and Q sample before the data
is processed along the signal chain.
The timing relationship between TxENABLE, PDCLK, and
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9958 | 制造商:AD 制造商全稱:Analog Devices 功能描述:2-Channel 500 MSPS DDS with 10-Bit DACs |
| AD9958 PCB | 制造商:Analog Devices 功能描述:EVAL BOARD ((NS)) |
| AD9958/PCB | 制造商:Analog Devices 功能描述:Evaluation Board For 2-Channel 500 MSPS DDS With 10-Bit DACs 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Analog Devices 功能描述:IC 10-BIT DAC DDS |
| AD9958/PCBZ | 功能描述:BOARD EVALUATION FOR AD9958 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:AgileRF™ 標(biāo)準(zhǔn)包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源 |
| AD9958/PCBZ | 制造商:Analog Devices 功能描述:EVAL BOARD, AD9958 DIRECT DIGITAL SYNTHE |
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