參數(shù)資料
型號(hào)： AD9957BSVZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 44/64頁(yè)
文件大?。?/td> 0K
描述： IC DDS 1GSPS 14BIT IQ 100TQFP
產(chǎn)品培訓(xùn)模塊： Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
標(biāo)準(zhǔn)包裝： 1
分辨率（位）： 14 b
主 fclk： 1GHz
調(diào)節(jié)字寬（位）： 32 b
電源電壓： 1.8V, 3.3V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 100-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝： 100-TQFP-EP（14x14）
包裝： 托盤
產(chǎn)品目錄頁(yè)面： 552 (CN2011-ZH PDF)
配用： AD9957/PCBZ-ND - BOARD EVAL AD9957 QUADRATURE MOD
Data Sheet
AD9957
Rev. C | Page 49 of 64
I/O_UPDATE, SYNC_CLK, AND SYSTEM CLOCK
RELATIONSHIPS
The I/O_UPDATE pin is used to transfer data from the serial
I/O buffer to the active registers in the device. Data in the buffer
is inactive.
SYNC_CLK is a rising edge active signal. It is derived from the
system clock and a divide-by-4 frequency divider. SYNC_CLK,
which is externally provided, can be used to synchronize
external hardware to the AD9957 internal clocks.
I/O_UPDATE initiates the start of a buffer transfer. It can
be sent synchronously or asynchronously relative to the
SYNC_CLK. If the setup time between these signals is met,
then constant latency (pipeline) to the DAC output exists.
For example, if repetitive changes to phase offset via the SPI
port is desired, the latency of those changes to the DAC output
is constant; otherwise, a time uncertainty of one SYNC_CLK
period is present.
By default, the I/O_UPDATE pin is an input that serves as a
strobe signal to allow synchronous update of the device oper-
ating parameters. A rising edge on I/O_UPDATE initiates
transfer of the register contents to the internal workings of
the device. Alternatively, the transfer of programmed data from
the programming registers to the internal hardware can be
accomplished by changing the state of the PROFILE[2:0] pins.
The timing diagram shown in Figure 64 depicts when the data
in the buffer is transferred to the active registers.
SYNC_CLK
SYSCLK
A
B
N
N + 1
N – 1
DATA IN
REGISTERS
DATA IN
I/O BUFFERS
N
N + 1
N + 2
I/O_UPDATE
THE DEVICE REGISTERS AN I/O UPDATE AT POINT A. THE DATA IS TRANSFERRED FROM THE ASYNCHRONOUSLY LOADED I/O BUFFERS AT POINT B.
06384-
161
Figure 64. I/O_UPDATE Transferring Data from I/O Buffer to Active Registers
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AD9957BSVZ-REEL 功能描述:IC DDS 1GSPS 14BIT IQ 100TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標(biāo)準(zhǔn)包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR)
AD9957BSVZREEL13 制造商:AD 制造商全稱:Analog Devices 功能描述:1 GSPS Quadrature Digital Upconverter w/18-Bit IQ Data Path and 14-Bit DAC
AD9958 制造商:AD 制造商全稱:Analog Devices 功能描述:2-Channel 500 MSPS DDS with 10-Bit DACs
AD9958 PCB 制造商:Analog Devices 功能描述:EVAL BOARD ((NS))
AD9958/PCB 制造商:Analog Devices 功能描述:Evaluation Board For 2-Channel 500 MSPS DDS With 10-Bit DACs 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Analog Devices 功能描述:IC 10-BIT DAC DDS
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