參數(shù)資料
型號(hào): AD9954
廠商: Analog Devices, Inc.
元件分類: XO, clock
英文描述: 400 MSPS 14-Bit, 1.8 V CMOS Direct Digital Synthesizer
中文描述: 400 MSPS的14位,1.8伏的CMOS直接數(shù)字頻率合成
文件頁(yè)數(shù): 34/36頁(yè)
文件大?。?/td> 1027K
代理商: AD9954
AD9954
Rev. 0 | Page 34 of 36
Table 13 indicates the logic level for each power-down bit that
drives out of the AD9954 core logic to the analog section and
the digital clock generation section of the chip for the external
power-down operation.
Layout Considerations
For the best performance, the following layout guidelines
should be observed. Always provide the analog power supply
(AVDD) and the digital power supply (DVDD) on separate
supplies, even if just from two different voltage regulators
driven by a common supply. Likewise, the ground connections
(AGND, DGND) should be kept separate as far back to the
source as possible (i.e., separate the ground planes on a local-
ized board, even if the grounds connect to a common point in
the system). Bypass capacitors should be placed as close to the
device pin as possible. Usually a multitiered bypassing scheme
consisting of a small high frequency capacitor (100 pF) placed
close to the supply pin and progressively larger capacitors
(0.1 μF, 10 μF) further back to the actual supply source works best.
Table 13. Power-Down Control Functions
Control
PWRDWNCTL = 0 CFR1<3> Don’t Care
Mode Active
Software Control
Description
Digital Power-Down = CFR1<7>
Comparator Power-Down = CFR1<6>
DAC Power-Down = CFR1<5>
Input Clock Power-Down = CFR1<4>
Digital Power-Down = 1’b1
Comparator Power-Down = 1’b0 Or CFR1<6>
DAC Power-Down = 1’b0
Input Clock Power-Down = 1’b0
Digital Power-Down = 1’b1
Comparator Power-Down = 1’b1
DAC Power-Down = 1’b1
Input Clock Power-Down = 1’b1
PWRDWNCTL = 1 CFR1<3> = 0
External Control,
Fast Recovery Power-Down Mode
PWRDWNCTL = 1 CFR1<3> = 1
External Control,
Full Power-Down Mode
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