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參數(shù)資料
| 型號： | AD9954 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | XO, clock |
| 英文描述： | 400 MSPS 14-Bit, 1.8 V CMOS Direct Digital Synthesizer |
| 中文描述： | 400 MSPS的14位，1.8伏的CMOS直接數(shù)字頻率合成 |
| 文件頁數(shù)： | 29/36頁 |
| 文件大小： | 1027K |
| 代理商： | AD9954 |
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AD9954
External Shaped On-Off Keying Mode Operation
Rev. 0 | Page 29 of 36
The external Shaped On-Off Keying mode is enabled by writing
CFR1<25> to a logic 1 AND writing CFR1<24> to a Logic 0.
When configured for external Shaped On-Off Keying, the
content of the ASFR becomes the scale factor for the data path.
The scale factors are synchronized to SYNC_CLK via the I/O
UPDATE functionality.
Synchronization; Register Updates (I/O UPDATE)
Functionality of the SYNC_CLK and I/O UPDATE
Data into the AD9954 is synchronous to the SYNC_CLK signal
(supplied externally to the user on the SYNC_CLK pin). The
I/O UPDATE pin is sampled on the rising edge of the
SYNC_CLK.
Internally, SYSCLK is fed to a divide-by-4 frequency divider to
produce the SYNC_CLK signal. The SYNC_CLK signal is pro-
vided to the user on the SYNC_CLK pin. This enables synchro-
nization of external hardware with the device’s internal clocks.
This is accomplished by forcing any external hardware to obtain
its timing from SYNC_CLK. The I/O UPDATE signal coupled
with SYNC_CLK is used to transfer internal buffer contents
into the control registers of the device. The combination of the
SYNC_CLK and I/O UPDATE pins provide the user with
constant latency relative to SYSCLK and also ensures phase
continuity of the analog output signal when a new tuning word
or phase offset value is asserted. Figure 23 demonstrates an I/O
UPDATE timing cycle and synchronization.
Notes to synchronization logic:
1)
The I/O UPDATE signal is edge detected to generate a
single rising edge clock signal that drives the register bank
flops. The I/O UPDATE signal has no constraints on duty
cycle. The minimum low time on I/O UPDATE is one
SYNC_CLK clock cycle.
2)
The I/O UPDATE pin is set up and held around the rising
edge of SYNC_CLK and has zero hold time and 4 ns setup
time.
0
SYSCLK
SDI
CS
SYNC_CLK
DISABLE
1
0
0
SCLK
TO CORE LOGIC
OSK
D
Q
PROFILE<1:0>
D
Q
I/O UPDATE
D
Q
÷ 4
SYNC_CLK
GATING
EDGE
DETECTION
LOGIC
REGISTER
MEMORY
I/O BUFFER
LATCHES
Figure 23. I/O Synchronization Block Diagram
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9954/PCB | 制造商:Analog Devices 功能描述:AD9954 400 MSPS DDS W/ 14 BIT DAC EVALBD - Bulk 制造商:Analog Devices 功能描述:EVALUATION KIT ((NS)) |
| AD9954/PCBZ | 功能描述:BOARD EVAL FOR 9954 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:AgileRF™ 標準包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源 |
| AD9954/PCBZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:400 MSPS, 14-Bit, 1.8 V CMOS, Direct Digital Synthesizer |
| AD9954_09 | 制造商:AD 制造商全稱:Analog Devices 功能描述:400 MSPS, 14-Bit, 1.8 V CMOS, Direct Digital Synthesizer |
| AD9954YSV | 制造商:Analog Devices 功能描述:Direct Digital Synthesizer 400MHz 1-DAC 14-Bit Serial 48-Pin TQFP EP 制造商:Rochester Electronics LLC 功能描述:400 MSPS DDS W/14 BIT DAC - Bulk 制造商:Analog Devices 功能描述:IC DDS 400MSPS SMD 9954 TQFP48 |
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