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參數(shù)資料
| 型號： | AD9953YSVZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 21/32頁 |
| 文件大小： | 0K |
| 描述： | IC DDS DAC 14BIT 1.8V 48TQFP |
| 產(chǎn)品培訓(xùn)模塊： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 標(biāo)準(zhǔn)包裝： | 500 |
| 分辨率（位）： | 14 b |
| 主 fclk： | 400MHz |
| 調(diào)節(jié)字寬（位）： | 32 b |
| 電源電壓： | 1.71 V ~ 1.96 V |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-TQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 48-TQFP 裸露焊盤（7x7） |
| 包裝： | 帶卷 (TR) |
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AD9953
Rev. A | Page 28 of 32
When the CFR1<3> bit is 0 and the PWRDWNCTL input pin is
high, the AD9953 is put into a fast recovery power-down mode.
In this mode, the digital logic and the DAC digital logic are
powered down. The DAC bias circuitry, PLL, oscillator, and
clock input circuitry is not powered down.
When the CFR1<3> bit is high, and the PWRDWNCTL input
pin is high, the AD9953 is put into the full power-down mode.
In this mode, all functions are powered down. This includes the
DAC and PLL, which take a significant amount of time to
power up.
When the PWRDWNCTL input pin is high, the individual
power-down bits (CFR1<7>, <5:4>) are invalid (Don’t Care)
and unused. When the PWRDWNCTL input pin is low, the
individual power-down bits control the power-down modes of
operation.
Note that the power-down signals are all designed such that a
Logic 1 indicates the low power mode and a Logic 0 indicates
the active or power-up mode.
Table 10 indicates the logic level for each power-down bit that
drives out of the AD9953 core logic to the analog section and
the digital clock generation section of the chip for the external
power-down operation.
Layout Considerations
For the best performance, the following layout guidelines
should be observed. Always provide the analog power supply
(AVDD) and the digital power supply (DVDD) on separate
supplies, even if just from two different voltage regulators
driven by a common supply. Likewise, the ground connections
(AGND, DGND) should be kept separate as far back to the
source as possible (i.e., separate the ground planes on a
localized board even if the grounds connect to a common point
in the system). Bypass capacitors should be placed as close to
the device pin as possible. Usually a multitiered bypassing
scheme consisting of a small high frequency capacitor (100 pF)
placed close to the supply pin and progressively larger capaci-
tors (0.1 μF, 10 μF) placed further away from the actual supply
source works best.
Table 10. Power-Down Control Functions
Control
Mode Active
Description
PWRDWNCTL = 0 CFR1<3> Don’t Care
Software Control
Digital Power-Down = CFR1<7>
DAC Power-Down = CFR1<5>
Input Clock Power-Down = CFR1<4>
PWRDWNCTL = 1 CFR1<3> = 0
External Control,
Fast Recovery Power-Down Mode
Digital Power-Down = 1’b1
DAC Power-Down = 1’b0
Input Clock Power-Down = 1’b0
PWRDWNCTL = 1 CFR1<3> = 1
External Control,
Full Power-Down Mode
Digital Power-Down = 1’b1
DAC Power-Down = 1’b1
Input Clock Power-Down = 1’b1
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9954 | 制造商:AD 制造商全稱:Analog Devices 功能描述:400 MSPS 14-Bit, 1.8 V CMOS Direct Digital Synthesizer |
| AD9954/PCB | 制造商:Analog Devices 功能描述:AD9954 400 MSPS DDS W/ 14 BIT DAC EVALBD - Bulk 制造商:Analog Devices 功能描述:EVALUATION KIT ((NS)) |
| AD9954/PCBZ | 功能描述:BOARD EVAL FOR 9954 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:AgileRF™ 標(biāo)準(zhǔn)包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源 |
| AD9954/PCBZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:400 MSPS, 14-Bit, 1.8 V CMOS, Direct Digital Synthesizer |
| AD9954_09 | 制造商:AD 制造商全稱:Analog Devices 功能描述:400 MSPS, 14-Bit, 1.8 V CMOS, Direct Digital Synthesizer |
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