參數(shù)資料
型號(hào)： AD9953YSVZ-REEL7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 17/32頁(yè)
文件大?。?/td> 0K
描述： IC DDS DAC 14BIT 1.8V 48TQFP
產(chǎn)品培訓(xùn)模塊： Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
標(biāo)準(zhǔn)包裝： 500
分辨率（位）： 14 b
主 fclk： 400MHz
調(diào)節(jié)字寬（位）： 32 b
電源電壓： 1.71 V ~ 1.96 V
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 48-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝： 48-TQFP 裸露焊盤（7x7）
包裝： 帶卷 (TR)
AD9953
Rev. A | Page 24 of 32
External Shaped On-Off Keying Mode Operation
The external shaped on-off keying mode is enabled by writing
CFR1<25> to a Logic 1 and writing CFR1<24> to a Logic 0.
When configured for external shaped on-off keying, the
content of the ASFR becomes the scale factor for the data path.
The scale factors are synchronized to SYNC_CLK via the
I/O UPDATE functionality.
Synchronization; Register Updates (I/O UPDATE)
Functionality of the SYNC_CLK and I/O UPDATE
Data into the AD9953 is synchronous to the SYNC_CLK signal
(supplied externally to the user on the SYNC_CLK pin). The
I/O UPDATE pin is sampled on the rising edge of the
SYNC_CLK.
Internally, SYSCLK is fed to a divide-by-4 freque
roduce the SYNC_CLK signal. The SYNC_CLK signal is
rovided to the user on the SYNC_CLK pin. This enables
ynchronization of external hardware with the device’s internal
ocks. This is accomplished by forcing any external hardware
obtain its timing from SYNC_CLK. The I/O UPDATE signal
coupled with SYNC_CLK is used to transfer internal buffer
contents into the control registers of the device. The combina-
tion of the SYNC_CLK and I/O UPDATE pins provides the
user with constant latency relative to SYSCLK, and also ensures
phase continuity of the analog output signal when a new tuning
word or phase offset value is asserted. Figure 21 demonstrates
an I/O UPDATE timing cycle and synchronization.
Notes for synchronization logic:
1.
The I/O UPDATE signal is edge detected to generate a
single rising edge clock signal that drives the register bank
flops. The I/O UPDATE signal has no constraints on duty
cycle. The minimum low time on I/O UPDATE is one
SYNC_CLK clock cycle.
2.
The I/O UPDATE pin is set up and held around the rising
C_CLK and has zero hold time and 4 ns setup
time.
SYSCLK
SYNC_CLK
DISABLE
ncy divider to
edge of SYN
p
s
cl
to
03374-0-006
SDI
0
10
÷ 4
OSK
PROFILE<1:0>
I/O UPDATE
SCLK
TO CORE LOGIC
CS
D
Q
D
Q
D
Q
SYNC_CLK
GATING
EDGE
DETECTION
LOGIC
REGISTER
MEMORY
I/O BUFFER
LATCHES
Figure 21. I/O Synchronization Block Diagram
相關(guān)PDF資料
PDF描述
AD9954YSVZ-REEL7 IC DDS DAC 14BIT 1.8V 48TQFP
AD9956YCPZ-REEL7 IC SYNTHESIZER 1.8V 48LFCSP
AD9957BSVZ-REEL IC DDS 1GSPS 14BIT IQ 100TQFP
AD9958BCPZ-REEL7 IC DDS DUAL 10BIT DAC 56LFCSP
AD9959BCPZ-REEL7 IC DDS QUAD 10BIT DAC 56LFCSP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9954 制造商:AD 制造商全稱:Analog Devices 功能描述:400 MSPS 14-Bit, 1.8 V CMOS Direct Digital Synthesizer
AD9954/PCB 制造商:Analog Devices 功能描述:AD9954 400 MSPS DDS W/ 14 BIT DAC EVALBD - Bulk 制造商:Analog Devices 功能描述:EVALUATION KIT ((NS))
AD9954/PCBZ 功能描述:BOARD EVAL FOR 9954 RoHS:是 類別:編程器，開(kāi)發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:AgileRF™ 標(biāo)準(zhǔn)包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源
AD9954/PCBZ1 制造商:AD 制造商全稱:Analog Devices 功能描述:400 MSPS, 14-Bit, 1.8 V CMOS, Direct Digital Synthesizer
AD9954_09 制造商:AD 制造商全稱:Analog Devices 功能描述:400 MSPS, 14-Bit, 1.8 V CMOS, Direct Digital Synthesizer
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*