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參數(shù)資料
| 型號： | AD9953 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | XO, clock |
| 英文描述： | 400 MSPS 14-Bit, 1.8V CMOS Direct Digital Synthesizer |
| 中文描述： | 400 MSPS的14位，1.8V CMOS的直接數(shù)字頻率合成器 |
| 文件頁數(shù)： | 12/42頁 |
| 文件大?。?/td> | 473K |
| 代理商： | AD9953 |
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PRELIMINARY TECHNICAL DATA
The modes of operation are summarized in the table below. Please note the PLL multiplier is
controlled via the CFR2<7:3> bits, independently of the CFR2<0> bit.
ClkModeSelect
CFR1<4>
CFR2<7:3>
AD9953
SYSTEM
CLOCK
F
clk
= F
osc
x M
F
clk
= F
osc
F
clk
= 0
F
clk
= F
ref
x M
F
clk
= F
ref
Frequency
Range (MHz)
80 < F
clk
< 400
20 < F
clk
< 30
F
clk
= 0
80 < F
clk
< 400
5 < F
clk
< 400
HIGH
HIGH
HIGH
LOW
LOW
LOW
LOW
HIGH
X
X
3 < M < 21
M < 4 or M > 20
X
3 < M < 21
M < 4 or M > 20
Table 2 Clock Input Modes of Operation
Phase Locked Loop (PLL)
The PLL allows multiplication of the REFCLK frequency. Control of the PLL is accomplished by
programming the 5-bit REFCLK Multiplier portion of Control Function Register #2, bits <7:3>.
When programmed for values ranging from 04h – 14h (4-20 decimal), the PLL multiplies the
REFCLK input frequency by the corresponding decimal value. The maximum output frequency of
the PLL is restricted to 400MHz, however. Whenever the PLL value is changed, the user should
be aware that time must be allocated to allow the PLL to lock (approximately 1ms).
The PLL is bypassed by programming a value outside the range of 4-20 (decimal). When
bypassed, the PLL is shut down to conserve power.
DAC Output
The AD9953 incorporates an integrated 14-bit current output DAC. Two complementary outputs
provide a combined full-scale output current (I
out
). Differential outputs reduce the amount of
common-mode noise that might be present at the DAC output, offering the advantage of an
increased signal-to-noise ratio. The full-scale current is controlled by means of an external resistor
(R
set
) connected between the DAC_Rset pin and the DAC ground (AGND). The full-scale current
is proportional to the resistor value as follows:
R
set
= 39.19/I
out
The maximum full-scale output current of the combined DAC outputs is 15mA, but limiting the
output to 10mA provides the best spurious-free-dynamic-range (SFDR) performance. The DAC
output compliance range is AVDD+0.250V to AVDD-375V. Voltages developed beyond this
range will cause excessive DAC distortion and could potentially damage the DAC output circuitry.
Proper attention should be paid to the load termination to keep the output voltage within this
compliance range.
Serial IO Port
REV. PrB 1/30/03
Page 12
Analog Devices, Inc.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9953ASV | 400 MSPS 14-Bit, 1.8V CMOS Direct Digital Synthesizer |
| AD9953PCB | 400 MSPS 14-Bit, 1.8V CMOS Direct Digital Synthesizer |
| AD9954 | 400 MSPS 14-Bit, 1.8 V CMOS Direct Digital Synthesizer |
| AD9954YSV | 400 MSPS 14-Bit, 1.8 V CMOS Direct Digital Synthesizer |
| AD9954YSV-REEL7 | 400 MSPS 14-Bit, 1.8 V CMOS Direct Digital Synthesizer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9953/PCB | 制造商:Analog Devices 功能描述:400 MSPS, 14BIT DGTL SYNTHESIZER - Bulk |
| AD9953ASV | 制造商:AD 制造商全稱:Analog Devices 功能描述:400 MSPS 14-Bit, 1.8V CMOS Direct Digital Synthesizer |
| AD9953PCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:400 MSPS 14-Bit, 1.8V CMOS Direct Digital Synthesizer |
| AD9953YSV | 制造商:Analog Devices 功能描述:Direct Digital Synthesizer 400MHz 1-DAC 14-Bit Serial 48-Pin TQFP EP 制造商:Rochester Electronics LLC 功能描述:AD9953 400 MSPS DDS W/ 14 BIT DAC - Bulk 制造商:Analog Devices 功能描述:IC DDS 400MSPS SMD 9953 TQFP48 |
| AD9953YSV-REEL7 | 制造商:Analog Devices 功能描述:Direct Digital Synthesizer 400MHz 1-DAC 14-Bit Serial 48-Pin TQFP EP T/R |
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