參數(shù)資料
型號: AD9913
廠商: Analog Devices, Inc.
元件分類: XO, clock
英文描述: Low Power 250 MSPS 10-Bit DAC 1.8 V CMOS Direct Digital Synthesizer
中文描述: 低功耗250 MSPS的10位DAC 1.8伏CMOS直接數(shù)字頻率合成器
文件頁數(shù): 22/32頁
文件大?。?/td> 473K
代理商: AD9913
AD9913
I/O PROGRAMMING
SERIAL PROGRAMMING
The AD9913 serial port is a flexible, synchronous serial
communications port allowing an easy interface to many
industry standard microcontrollers and microprocessors. The
serial I/O is compatible with most synchronous transfer
formats, including both the Motorola 6905/11 SPI and Intel
8051 SSR protocols.
The interface allows read/write access to all registers that
configure the AD9913. MSB first or LSB first transfer formats
are supported. The AD9913 serial interface port is configured
as a single pin I/O (SDIO), which allows a two-wire interface.
The AD9913 does not have a SDO pin for 3-wire operation.
With the AD9913, the instruction byte specifies read/write
operation and the register address. Serial operations on the
AD9913 occur only at the register level, not the byte level.
For the AD9913, the serial port controller recognizes the
instruction byte register address and automatically generates
the proper register byte address. In addition, the controller
expects that all bytes of that register are accessed. It is a
requirement that all bytes of a register be accessed during
serial I/O operations.
There are two phases to a communication cycle with the
AD9913. Phase 1 is the instruction cycle, which is the writing of
an instruction byte into the AD9913, coincident with the first
Rev. 0 | Page 22 of 32
eight SCLK rising edges. The instruction byte provides the
AD9913 serial port controller with information regarding the
data transfer cycle, which is Phase 2 of the communication
cycle. The Phase 1 instruction byte defines whether the
upcoming data transfer is read or write and the serial address of
the register being accessed.
The first eight SCLK rising edges of each communication cycle
are used to write the instruction byte into the AD9913. The
remaining SCLK edges are for Phase 2 of the communication
cycle. Phase 2 is the actual data transfer between the AD9913
and the system controller. The number of bytes transferred
during Phase 2 of the communication cycle is a function of the
register accessed. For example, when accessing the Control
Function Register 2, which is two bytes wide, Phase 2 requires
that two bytes be transferred. If accessing one of the profile
registers, which are six bytes wide, Phase 2 requires that six
bytes be transferred. After transferring all data bytes per the
instruction, the communication cycle is completed.
At the completion of any communication cycle, the AD9913
serial port controller expects the next eight rising SCLK edges
to be the instruction byte of the next communication cycle.
All data input to the AD9913 is registered on the rising edge
of SCLK. All data is driven out of the AD9913 on the falling
edge of SCLK. Figure 30 through Figure 32 illustrate the general
operation of serial ports.
I
7
SDIO
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
SCLK
CS
I
6
I
5
I
4
I
3
I
2
I
1
I
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
0
Figure 30. Serial Port Writing Timing—Clock Stall Low
I
7
SDIO
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
SCLK
CS
I
6
I
5
I
4
I
3
I
2
I
1
I
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
0
Figure 31. Serial Port Write Timing—Clock Stall High
I
7
SDIO
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
SCLK
CS
I
6
I
5
I
4
I
3
I
2
I
1
I
0
D
O7
D
O6
D
O5
D
O4
D
O3
D
O2
D
O1
D
O0
0
Figure 32. Two-Wire Serial Port Read Timing—Clock Stall High
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