參數(shù)資料
型號(hào)： AD9913
廠商： Analog Devices, Inc.
元件分類(lèi)： XO, clock
英文描述： Low Power 250 MSPS 10-Bit DAC 1.8 V CMOS Direct Digital Synthesizer
中文描述： 低功耗250 MSPS的10位DAC 1.8伏CMOS直接數(shù)字頻率合成器
文件頁(yè)數(shù)： 12/32頁(yè)
文件大?。?/td> 473K
代理商： AD9913
AD9913
THEORY OF OPERATION
DDS CORE
The DDS block generates a reference signal (sine or cosine
based on the selected DDS sine output bit). The parameters of
the reference signal (frequency and phase), are applied to the
DDS at its frequency and phase offset control inputs, as shown
in Figure 19.
Rev. 0 | Page 12 of 32
0
SYSTEM
CLOCK
32
15
FREQUENCY
CONTROL
ANGLE
TO
AMPLITUDE
CONVERSION
(SINE OR
COSINE)
PHASE
OFFSET
CONTROL
TO DAC
MSBs
D Q
R
ACCUMULATOR
RESET
32
MSB ALIGNED
DDS SIGNAL CONTROL PARAMETERS
10
15
32
32
14
32-BIT
ACCUMULATOR
Figure 19. DDS Block Diagram
The output frequency (f
OUT
) of the AD9913 is controlled by the
frequency tuning word (FTW) at the frequency control input to
the DDS. In all modes except for programmable modulus, the
relationship between f
OUT
, FTW, and f
SYSCLK
is:
SYSCLK
OUT
f
FTW
32
2
f
=
(1)
where
FTW
is a 32-bit integer ranging in value from 0 to
2,147,483,647 (2
31
1), which represents the lower half of the
full 32-bit range. This range constitutes frequencies from dc to
Nyquist (that is, f
SYSCLK
).
The FTW required to generate a desired value of
f
OUT
is found
by solving Equation 1 for FTW as given in Equation 2
=
SYSCLK
OUT
f
f
FTW
32
2
round
(2)
where the round
(x)
function rounds the argument (the value of
x) to the nearest integer. This is required because the FTW is
constrained to be an integer value.
For applications where rounding to the nearest available fre-
quency is not acceptable, programmable modulus mode enables
additional options.
The relative phase of the DDS signal can be digitally controlled
by means of a 14-bit phase offset word (POW). The phase offset
is applied prior to the angle-to-amplitude conversion block
internal to the DDS core. The relative phase offset (Δθ) is given by
π
=
θ
Δ
14
14
2
360
2
POW
2
POW
where the upper quantity is for the phase offset expressed as
radian units and the lower quantity as degrees. To find the
POW value necessary to develop an arbitrary Δθ, solve the
above equation for POW and round the result (in a manner
similar to that described for finding an arbitrary FTW in
Equation 1 and Equation 2).
FTW
POW
1
0
EXTERNAL
INTERNAL
REGISTER MAP AND TIMING CONTROL
+
DAC
IOUT
IOUT
RSET
DDS CORE
I/O PORT
CLOCK PORT
R
R
PLL
MULTIPLIER
CLOCK
SELECTION
S
C
S
A
M
P
I
S
1
0
1
0
PROFILE
SELECTIONS
1
0
1
0
Z
–1
AUXILIARY
ACCUMULATOR
ANGLE TO
AMPLITUDE
PHASE
ACCUMULATOR
PHASE
OFFSET
0
S
32
32
32
32
32
14
14
10
2
Figure 20. Detailed Block Diagram
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9913/PCBZ 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開(kāi)發(fā)工具 Sub 50mW 250MSPS (+) 10-bit DDS RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類(lèi)型:ADC 工具用于評(píng)估:ADS130E08 接口類(lèi)型:SPI 工作電源電壓:- 6 V to + 6 V
AD9913/PCBZ1 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:Low Power 250 MSPS 10-Bit DAC 1.8 V CMOS Direct Digital Synthesizer
AD9913BCPZ 功能描述:IC DDS 10BIT DAC 250MSPS 32LFCSP RoHS:是 類(lèi)別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標(biāo)準(zhǔn)包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類(lèi)型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR)
AD9913BCPZ1 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:Low Power 250 MSPS 10-Bit DAC 1.8 V CMOS Direct Digital Synthesizer
AD9913BCPZ-REEL7 功能描述:IC DDS 250MSPS 10BIT ADC 32LFCSP RoHS:是 類(lèi)別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標(biāo)準(zhǔn)包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類(lèi)型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR)
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