參數(shù)資料
型號： AD9910BSVZ
廠商： Analog Devices Inc
文件頁數(shù)： 20/64頁
文件大?。?/td> 0K
描述： IC DDS 1GSPS 14BIT PAR 100TQFP
產(chǎn)品培訓(xùn)模塊： Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
設(shè)計(jì)資源： Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121)
標(biāo)準(zhǔn)包裝： 1
分辨率（位）： 14 b
主 fclk： 1GHz
調(diào)節(jié)字寬（位）： 32 b
電源電壓： 1.8V, 3.3V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 100-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝： 100-TQFP-EP（14x14）
包裝： 托盤
產(chǎn)品目錄頁面： 552 (CN2011-ZH PDF)
Data Sheet
AD9910
Rev. D | Page 27 of 64
External PLL Loop Filter Components
The PLL_LOOP_FILTER pin provides a connection interface to
attach the external loop filter components. The ability to use
custom loop filter components gives the user more flexibility to
optimize the PLL performance. The PLL and external loop filter
components are shown in Figure 35.
PFD
CP
PLL_LOOP_FILTER
VCO
÷N
PLL OUT
PLL IN
AVDD
REFCLK PLL
2
R1
C1
C2
06479-
016
Figure 35. REFCLK PLL External Loop Filter
In the prevailing literature, this configuration yields a third-
order, Type II PLL. To calculate the loop filter component
values, begin with the feedback divider value (N), the gain of
the phase detector (KD), and the gain of the VCO (KV) based on
the programmed VCO SEL bit settings (see Table 1 for KV). The
loop filter component values depend on the desired open-loop
bandwidth (fOL) and phase margin (φ), as follows:
( )
+
=
φ
K
Nf
π
R1
V
D
OL
sin
1
(4)
( )
( )2
2
tan
OL
V
D
f
π
N
φ
K
C1 =
(5)
(
)
( )
( )
=
φ
f
π
N
K
C2
OL
V
D
cos
sin
1
2
(6)
where:
KD is equal to the programmed value of ICP.
KV is taken from Table 1.
Ensure that proper units are used for the variables in Equation 4
through Equation 6. ICP must be in amps, not microamps (μA)
as appears in Table 9; KV must be in hertz per volts (Hz/V), not
megahertz per volts (MHz/V) as listed in Table 1; the loop
bandwidth (fOL) must be in hertz (Hz); the phase margin (φ)
must be in radians.
For example, suppose the PLL is programmed such that ICP =
287 μA, KV = 625 MHz/V, and N = 25. If the desired loop
bandwidth and phase margin are 50 kHz and 45°, respectively,
then the loop filter component values are R1 = 52.85 , C1 =
145.4 nF, and C2 = 30.11 nF.
PLL LOCK INDICATION
When the PLL is in use, the PLL_LOCK pin provides an active
high indication that the PLL has locked to the REFCLK input
signal. Note that the PLL_LOCK pin is a latched output. When the
PLL is bypassed, the pin may remain at Logic 1. The PLL_LOCK
pin can be cleared by setting the PFD reset bit. The PFD reset
bit must be cleared for normal operation.
OUTPUT SHIFT KEYING (OSK)
The OSK function (see Figure 36) allows the user to control the
output signal amplitude of the DDS. Both a manual and an
automatic mode are available under program control. The
amplitude data generated by the OSK block has priority over
any other functional block that is programmed to deliver
amplitude data to the DDS. Therefore, the OSK data source,
when enabled, overrides all other amplitude data sources.
06479-
017
OSK ENABLE
AMPLITUDE SCALE FACTOR
(ASF[15:2])
AMPLITUDE RAMP RATE
(ASF[31:16])
AMPLITUDE STEP SIZE
(ASF[1:0])
MANUAL OSK EXTERNAL
AUTO OSK ENABLE
OSK
DDS CLOCK
TO DDS
AMPLITUDE
CONTROL
PARAMETER
60
LOAD ARR AT I/O_UPDATE
OSK
CONTROLLER
14
16
14
2
Figure 36. OSK Block Diagram
The operation of the OSK function is governed by two CFR1
register bits (OSK enable and select auto OSK), the external
OSK pin, and the entire 32 bits of the ASF register. The primary
control for the OSK block is the OSK Enable bit. When the OSK
function is disabled, the OSK input controls are ignored and the
internal clocks shut down.
When the OSK function is enabled, automatic or manual
operation is selected using the select auto OSK bit. A Logic 0
indicates manual mode (default).
Manual OSK
In manual mode, output amplitude is varied by successive write
operations to the amplitude scale factor portion of the ASF
register. The rate at which amplitude changes can be applied to
the output signal is limited by the speed of the serial I/O port.
In manual mode, the OSK pin functionality depends on the
state of the manual OSK external control bit. When the OSK
pin is Logic 0, the output amplitude is forced to 0; otherwise,
the output amplitude is set by the amplitude scale factor value.
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