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| 型號： | AD9910BSVZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 19/64頁 |
| 文件大小： | 0K |
| 描述： | IC DDS 1GSPS 14BIT PAR 100TQFP |
| 產(chǎn)品培訓(xùn)模塊： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 設(shè)計(jì)資源： | Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 分辨率（位）： | 14 b |
| 主 fclk： | 1GHz |
| 調(diào)節(jié)字寬（位）： | 32 b |
| 電源電壓： | 1.8V, 3.3V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-TQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 100-TQFP-EP（14x14） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 552 (CN2011-ZH PDF) |
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AD9910
Data Sheet
Rev. D | Page 26 of 64
as well as a programmable charge pump current and external
loop filter components (connected via the PLL_LOOP_FILTER
pin). These features add an extra layer of flexibility to the PLL,
allowing optimization of phase noise performance and
flexibility in frequency plan development. The PLL is also
equipped with a PLL_LOCK pin.
The PLL output frequency range (fSYSCLK) is constrained to the
range of 420 MHz ≤ fSYSCLK ≤ 1 GHz by the internal VCO. In
addition, the user must program the VCO to one of six operating
and Figure 34 summarize these VCO ranges.
Figure 33 shows the boundaries of the VCO frequency ranges
over the full range of temperature and supply voltage variation
for all devices from the available population. The implication is
that multiple devices chosen at random from the population and
operated under widely varying conditions may require different
values to be programmed into CFR3[26:24] to operate at the
same frequency. For example, Part A chosen randomly from the
population, operating at an ambient temperature of 10°C with
a system clock frequency of 900 MHz may require CFR3[26:24] to
be set to 100b, whereas Part B chosen randomly from the
population, operating at an ambient temperature of 90°C with a
system clock frequency of 900 MHz may require CFR3[26:24]
to be set to 101b. If a frequency plan is chosen such that the
system clock frequency operates within one set of boundaries
(as shown in Figure 33), the required value in CFR3[26:24] is
consistent from part to part.
Figure 34 shows the boundaries of the VCO frequency ranges
over the full range of temperature and supply voltage variation
for an individual device selected from the population. Figure 34
shows that the VCO frequency ranges for a single device always
overlap when operated over the full range of conditions.
If a user wants to retain a single default value for CFR3[26:24],
a frequency that falls into one of the ranges found in Figure 33
should be selected. Additionally, for any given individual device,
the VCO frequency ranges overlap, meaning that any given
device exhibits no gaps in its frequency coverage across VCO
ranges over the full range of conditions.
06479-
059
VCO0
VCO1
VCO2
VCO3
VCO4
VCO5
395
495
595
695
795
895
995
fLOW = 400
fHIGH = 460
fLOW = 455
fHIGH = 530
fLOW = 530
fHIGH = 615
fLOW = 760
fHIGH = 875
fLOW = 920
fHIGH = 1030
fLOW = 650
fHIGH = 790
(MHz)
Figure 33. VCO Ranges Including Atypical Wafer Process Skew
335
435
535
635
735
835
935
1035
1135
VCO0
VCO1
VCO2
VCO3
VCO4
VCO5
06479-
060
fLOW = 370
fHIGH = 510
fLOW = 420
fHIGH = 590
fLOW = 500
fHIGH = 700
fLOW = 700
fHIGH = 950
fLOW = 820
fHIGH = 1150
fLOW = 600
fHIGH = 880
(MHz)
Figure 34. Typical VCO Ranges
Table 8. VCO Range Bit Settings
VCO SEL Bits (CFR3[26:24])
VCO Range
000
VCO0
001
VCO1
010
VCO2
011
VCO3
100
VCO4
101
VCO5
110
PLL bypassed
111
PLL bypassed
PLL Charge Pump
The charge pump current (ICP) is programmable to provide the
user with additional flexibility to optimize the PLL performance.
Table 9 lists the bit settings vs. the nominal charge pump current.
Table 9. PLL Charge Pump Current
I
CP Bits (CFR3[21:19])
Charge Pump Current, I
CP (μA)
000
212
001
237
010
262
011
287
100
312
101
337
110
363
111
387
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| AD9910BSVZ | 制造商:Analog Devices 功能描述:IC DDS 1GHZ TQFP-100 制造商:Analog Devices 功能描述:IC, DDS, 1GHZ, TQFP-100 |
| AD9910BSVZ-REEL | 功能描述:IC DDS 1GSPS 14BIT PAR 100TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標(biāo)準(zhǔn)包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD9911 | 制造商:AD 制造商全稱:Analog Devices 功能描述:500 MSPS Direct Digital Synthesizer with 10-Bit DAC |
| AD9911/PCB | 制造商:Analog Devices 功能描述:500 MSPS DIRECT DGTL SYNTHESIZER W/ 10-BIT DAC AD9911/PCB - Bulk |
| AD9911/PCBZ | 功能描述:BOARD EVAL FOR AD9911 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:AgileRF™ 標(biāo)準(zhǔn)包裝:1 系列:PCI Express® (PCIe) 主要目的:接口，收發(fā)器，PCI Express 嵌入式:- 已用 IC / 零件:DS80PCI800 主要屬性:- 次要屬性:- 已供物品:板 |
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