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| 型號： | AD9895KBCZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 10/58頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CCD SIGNAL PROC/GEN 64-CSPBGA |
| 標準包裝： | 1 |
| 類型： | CCD 信號處理器，12 位 |
| 輸入類型： | 邏輯 |
| 輸出類型： | 邏輯 |
| 接口： | 3 線串口 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFBGA，CSPBGA |
| 供應商設備封裝： | 64-CSPBGA（9x9） |
| 包裝： | 托盤 |
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REV. A
–18–
AD9891/AD9895
Individual Vertical Sequences
To generate the individual vertical sequences or patterns shown
in Figure 18, five registers are required for each sequence.
Table VII summarizes these registers and their respective bit
lengths. The start polarity (VTPPOL) determines the starting
polarity of the vertical sequence and can be programmed high
or low. The first toggle position (VTPTOG1) and second
toggle position (VTPTOG2) are the pixel locations within the line
where the pulse transitions. A third toggle position
(VTPTOG3) is also available for sequences 0 through 7. All
toggle positions are 10-bit values, which limits the placement of
a pulse to within 1024 pixels of a line. A separate register,
VSTART, sets the start position of the sequence within the line
(see Individual Vertical Regions section). The Length
(VTPLEN) Register determines the number of pixels between
each of the pulse repetitions, if any repetitions have been
programmed. The number of repetitions (VTPREP) simply
determines the number of pulse repetitions desired within a
single line. Programming “1” for VTPREP gives a single
pulse, while setting to “0” will provide a fixed dc output based
on the start polarity value. There is a total of 12 individual
sequences that may be programmed.
When specifying the individual regions, each sequence may be
assigned to any of the V1–V4 outputs. For example, Figure 19
shows a typical 4-phase V-clock arrangement. Two different
sequences are needed to generate the different pulsewidths.
The use of individual start positions for V1–V4 allows the four
outputs to be generated from two sequences. Figure 20 shows a
slightly different V-clock arrangement in which V2, V3, and V4
are simply shifted and/or inverted versions of V1. Only one
individual sequence is needed because all signals have the same
pulsewidth. The invert sequence registers (VINV) are used for
V3 and V4 (see Table VII).
Note that for added flexibility, the VTPPOL Registers (Start
Polarity) may be used as an extra toggle position.
Table VII. Individual VTP Sequence Parameters
Register
Length
Range
Description
VTPPOL
1b
High/Low
Starting Polarity of Vertical Transfer Pulse for Each Sequence 0–11
VTPTOG1
10b
0–1023 Pixel Location
First Toggle Position within Line for Each Sequence 0–11
VTPTOG2
10b
0–1023 Pixel Location
Second Toggle Position within Line for Each Sequence 0–11
VTPTOG3
10b
0–1023 Pixel Location
Third Toggle Position within Line for Each Sequence 0–7
VTPLEN
10b
0–1023 Pixels
Length between Pulse Repetitions for Each Sequence 0–11
VTPREP
12b
0–4095 Pulses
Number of Pulse Repetitions for Each Sequence 0–11 (0 = DC Output)
HD
V1–V4
PROGRAMMABLE SETTINGS FOR EACH SEQUENCE:
1: START POLARITY
2: 1ST TOGGLE POSITION
3: 2ND TOGGLE POSITION (THERE IS ALSO A 3RD TOGGLE POSITION AVAILABLE FOR SEQUENCES 0 TO 7)
4: LENGTH BETWEEN REPEATS
5: NUMBER OF REPEATS
START POSITION OF SEQUENCE IS INDIVIDUALLY PROGRAMMABLE FOR EACH V1–V4 OUTPUT
4
5
1
2
3
Figure 18. Individual Vertical Sequence Programmability
V1
V2
V1 USES SEQUENCE 0
V3
V4
HD
V2 USES SEQUENCE 0,
WITH DIFFERENT START POSITION
V3 USES SEQUENCE 1
V4 USES SEQUENCE 1,
WITH DIFFERENT START POSITION
Figure 19. Example of Separate V1–V4 Signals Using Two Individual Sequences
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| AD9895KBCZRL | 功能描述:IC CCD SIGNAL PROC/GEN 64-CSPBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 傳感器和探測器接口 系列:- 其它有關文件:Automotive Product Guide 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:74 系列:- 類型:觸控式傳感器 輸入類型:數(shù)字 輸出類型:數(shù)字 接口:JTAG，串行 電流 - 電源:100µA 安裝類型:表面貼裝 封裝/外殼:20-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:20-TSSOP 包裝:管件 |
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