參數(shù)資料
型號(hào)： AD9895KBCZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 22/58頁(yè)
文件大?。?/td> 0K
描述： IC CCD SIGNAL PROC/GEN 64-CSPBGA
標(biāo)準(zhǔn)包裝： 1
類型： CCD 信號(hào)處理器，12 位
輸入類型： 邏輯
輸出類型： 邏輯
接口： 3 線串口
安裝類型： 表面貼裝
封裝/外殼： 64-VFBGA，CSPBGA
供應(yīng)商設(shè)備封裝： 64-CSPBGA（9x9）
包裝： 托盤
REV. A
AD9891/AD9895
–29–
VD
SUBCK
t
EXP
VSUB
MECHANICAL
SHUTTER
OPEN
CLOSED
MODE 0
MODE 1
MSHUT
STROBE
SERIAL
WRITES
OPEN
VSG
IMAGE READOUT
ODD
EVEN
Figure 35. Exposure and Readout of Interlaced Frame
Example of Exposure and Readout of Interlaced Frame
Figure 35 shows the sequence of events for a typical exposure and
readout operation using a mechanical shutter and strobe. The
register values for the VSUB, MSHUT, and STROBE toggle
positions may be previously loaded at any time, prior to triggering
these functions. Additional register writes are required to configure
the vertical clock outputs, V1–V4, which are not described here.
0: Write to the READOUT Register (Addr x281) to specify
the number of fields to further suppress SUBCK while the
CCD data is readout. In this example, READOUT = 2.
1: Write to the EXPOSURE Register (Addr x27D) to start the
exposure and specify the number of fields to suppress
SUBCK and VSG outputs during exposure. In this example,
EXPOSURE = 2.
Write to the TRIGGER Register (Addr x280) to enable the
STROBE, MSHUT, and VSUB signals. To trigger all three
signals (as in Figure 36) the register TRIGGER = 7.
Write to the SGACTLINE Register (Addr x265 and
Addr x266) and SGMASK Register (Addr x26F and
Addr x270) to configure the sensor gates for ODD field
readout (interlaced CCD).
2: VD/HD falling edge will update the serial writes from 1.
3: If VSUB Mode = 0, VSUB output turns ON at the line
specified in the VSUBON Register (Addr x272 and
Addr x273).
STROBE output turns ON at the location specified in the
STROBON Registers (Addr x294 to Addr x299).
4: STROBE output turns OFF at the location specified in the
STROBEOFF Registers (Addr x29A to Addr x29F).
5: MSHUT Output turns OFF at the location specified in the
MSHUTOFF Registers (Addr x28D to Addr x292).
6: Write to the SGACTLINE Register (Addr x253 and
Addr x254) and SGMASK Register to configure the sensor
gates for EVEN field readout.
7: VD/HD falling edge will update the serial writes from 6.
8: Write to the SGACTLINE Register and SGMASK Register
to reconfigure the sensor gates for Draft/Preview Mode output.
Write to the MSHUTON Register (Addr x287) to reopen
the mechanical shutter for Draft/Preview Mode.
9: VD/HD falling edge will update the serial writes from 8.
10: VSG outputs returns to Draft/Preview Mode timing.
SUBCK output resumes operation.
MSHUT output returns to the ON position (Active or
“Open”).
VSUB output returns to the OFF position (Inactive).
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