參數(shù)資料
型號: AD9854
廠商: Analog Devices, Inc.
元件分類: XO, clock
英文描述: CMOS 300MHz Quadrature Complete-DDS
中文描述: 300MHz CMOS正交DDS數(shù)字合成器
文件頁數(shù): 28/28頁
文件大?。?/td> 589K
代理商: AD9854
AD9854 PRELIMINARY TECHNICAL DATA
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7/16/99 REV.PRA
28
CR[11:9] are the three bits that describe the five operating
modes of the AD9854/52:
0h = single tone mode
1h = fsk mode
2h = ramped fsk mode
3h = chirp mode
4h = psk mode
CR[8] is the internal update active bit. When this bit is set
to logic 1, the UPDATE_CLOCK pin is an output and the
AD9854/52 generates the UPDATE_CLK signal. When
logic 0, external update_clock functionality is performed,
the UPDATE_CLK pin is configured as an input.
CR[7] is open
CR[6] is the bypass the inverse sinc filter bit. When set,
the data from the DDS block goes directly to the output
ramp logic and the clock to the inverse sinc filter is
stopped. Default is clear, filter enabled.
CR[5] is the output amplitude enable bit. When set the
output ramping function is enabled and is performed in
accordance with the CR[4] bit requirements.
CR[4] is the internal/external output ramp control bit.
When set, logic 1, the output ramp factor will be internally
generated and applied to both the I and Q paths, When
clear, the output ramping function is externally controlled
by the user and the ramp factor is the I and Q output ramp
factor register values. Defaults low external ramp factors
used. The two registers that are the ramp factors also
default low such that the output is off at power up and until
the device is programmed by the user.
CR[3:2] are open.
CR[1] is the serial port msb/lsb first bit. Defaults low, msb
first.
CR[0] is the serial port SDO active bit. Defaults low,
inactive.
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