參數(shù)資料
型號(hào): AD9854
廠商: Analog Devices, Inc.
元件分類: XO, clock
英文描述: CMOS 300MHz Quadrature Complete-DDS
中文描述: 300MHz CMOS正交DDS數(shù)字合成器
文件頁(yè)數(shù): 18/28頁(yè)
文件大?。?/td> 589K
代理商: AD9854
AD9854 PRELIMINARY TECHNICAL DATA
_____________________________________________________________________________________________________
7/16/99 REV.PRA
18
Parallel
Address
Hex
Serial
Address
AD9854/52 Register Layout
Hex
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default
Value
00h
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
0
Phase Adjust Register #1 <13:8> (Bits 15, 14 open) Phase 1
Phase Adjust Register #1 <7:0>
Phase Adjust Register #2 <13:8:> (Bits 15, 14 open) Phase 2
Phase Adjust Register #2 <7:0>
Frequency Tuning Word 1 <47:0> Frequency 1
Frequency Tuning Word 1 <39:32>
Frequency Tuning Word 1 <31:24>
Frequency Tuning Word 1 <23:16>
Frequency Tuning Word 1 <15:8>
Frequency Tuning Word 1 <7:0>
Frequency Tuning Word 2 <47:40> Frequency 2
Frequency Tuning Word 2 <39:32>
Frequency Tuning Word 2 <31:24>
Frequency Tuning Word 2 <23:16>
Frequency Tuning Word 2 <15:8>
Frequency Tuning Word 2 <7:0>
Delta Frequency Word <47:40>
Delta Frequency Word <39:32>
Delta Frequency Word <31:24>
Delta Frequency Word <23:16>
Delta Frequency Word <15:8>
Delta Frequency Word <7:0>
Update Clock <31:24>
Update Clock <23:16>
Update Clock <15:8>
Update Clock <7:0>
Ramp Rate Clock <19:16> (Bits 23, 22, 21, 20 open)
Ramp Rate Clock <15:8>
Ramp Rate Clock <7:0>
Open
Open
Open
CompPD
1
00h
2
000000h
3
000000h
4
00000h
5
64(dec)
6
000h
PLL PD
QDAC
PD
Ref Mult
2
Mode 1
DAC PD
DIG PD
00h
Open
PLL
Range
CLR
Acc 2
Bypass
PLL
Triangle
Ref Mult
4
SRC
QDAC
Ref Mult
3
Mode 2
Ref Mult
1
Mode 0
Ref Mult
0
Int Update
Clk
64h
CLR
Acc
1
Open
01h
1E
1F
20
7
Bypas
s Inv
Sinc
OSK EN
OSK
INT
Open
Open
LSB First
SDO
Active
20h
21
22
8
Output Shape Key 1 Mult <11:8> (Bits 15, 14, 13, 12 open)
Output Shape Key 1 Mult <7:0>
000h
23
24
9
Output Shape Key Q Mult <11:8> (Bits 15, 14, 13, 12 open)
Output Shape Key Q Mult <7:0>
000h
25
A
Output Shape Key Ramp Rate <7:0>
128(dec)
26
27
B
QDAC <11:8> (Bits 15, 14, 13, 12 open)
QDAC <7:0>
Table 1: Register Layout. Shaded bits above comprise the “Control Register”
00h
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