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參數(shù)資料
| 型號(hào)： | AD9854 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | XO, clock |
| 英文描述： | CMOS 300MHz Quadrature Complete-DDS |
| 中文描述： | 300MHz CMOS正交DDS數(shù)字合成器 |
| 文件頁(yè)數(shù)： | 13/28頁(yè) |
| 文件大小： | 589K |
| 代理商： | AD9854 |
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AD9854 PRELIMINARY TECHNICAL DATA
_____________________________________________________________________________________________________
Keying”. The output of this counter is
clocking the
48-bit Frequency Accumulator
shown as “Accu 1” below. The Ramp Rate
Clock determines the time spent at each
intermediate frequency between F1 and F2.
The “dwell time” spent at F1 and F2 is
determined by the duration that the FSK input
pin, pin 29, is held high or low after the
destination frequency has been reached.
7/16/99 REV.PRA
13
Register addresses 10 – 15 hex are for the
48-
bit “Delta Frequency Word
”. This 48-bit
word is accumulated (added to itself) every
time it receives a pulse from the ramp rate
clock. The output of this accumulator is added
to or subtracted from the F1 or F2 frequency
word which is fed to the input of the
48-bit
Phase Accumulator
that forms the numerical
phase steps for the sine and cosine wave
output. In this fashion, the output frequency is
ramped-up and down according to the state of
Pin 29 and the speed at which this happens is a
function of the 20-bit ramp rate clock. Once
the destination frequency is achieved, the ramp
rate clock is stopped and this halts the
frequency accumulation process.
The control register contains a
Triangle Bit
at
register address 1F. Setting the bit high causes
an automatic ramp-up and ramp-down
between F1 and F2 without having to toggle
Pin 29. This uses the ramp-rate-clock time
period and the delta-frequency-word step size
to form a continuously sweeping linear ramp
from F1 to F2 and back to F1. This is not
FSK or ramped FSK; it is an easily
implemented function that users may find
useful for linear frequency sweeping of the
DDS output.
To make the linear, ramped FSK mode even
more flexible, users can change the 48-bit delta
frequency word and/or the 20-bit ramp-rate
counter
on-the-fly
(during the ramping from
F1 to F2). To create
non-linear
frequency
changes it is necessary to combine several
linear ramps in a
piece-wise
fashion whose
slopes are different. This is done by starting a
linear ramp at some rate or “slope” and then
changing the slope (by changing the ramp rate
clock or delta frequency word or both) as often
as necessary to form the desired non-linear
frequency response before the destination
frequency has been reached. These changes
can be precisely timed using the
32-bit
Internal Update Clock
(see detailed
description elsewhere in this data sheet).
48-Bit Delta-
Frequency
Word
Accu 1
Accu 2
Frequency
Tuning
Word 1
20-Bit
Ramp Rate
Clock
System
Clock
Out
Frequency
Tuning
Word 2
FSK
(pin 29)
ADDER
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9854/PCB | 制造商:Analog Devices 功能描述:Evaluation Board For IC Digital Synthesizer Single 制造商:Analog Devices 功能描述:Direct Digital Synthesizer IC (DDS) |
| AD9854/PCBZ | 功能描述:BOARD EVAL FOR AD9854 RoHS:是 類別:編程器，開(kāi)發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:AgileRF™ 標(biāo)準(zhǔn)包裝:1 系列:PCI Express® (PCIe) 主要目的:接口，收發(fā)器，PCI Express 嵌入式:- 已用 IC / 零件:DS80PCI800 主要屬性:- 次要屬性:- 已供物品:板 |
| AD9854ASQ | 制造商:Analog Devices 功能描述:IC DDS SYNTHESIZER |
| AD9854ASQZ | 制造商:Analog Devices 功能描述:Direct Digital Synthesizer 300MHz 2-DAC 12-Bit Parallel/Serial 80-Pin LQFP 制造商:Analog Devices 功能描述:Communication IC |
| AD9854AST | 制造商:Analog Devices 功能描述:Direct Digital Synthesizer 300MHz 2-DAC 12-Bit Parallel/Serial 80-Pin LQFP Tray 制造商:Rochester Electronics LLC 功能描述:200 MHZ QUADRATURE DDS SYNTHESIZER - Tape and Reel 制造商:Analog Devices 功能描述:IC SEMICONDUCTOR ((NS)) |
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