參數(shù)資料
型號(hào)： AD9852ASVZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 26/52頁(yè)
文件大小： 0K
描述： IC DDS SYNTHESIZER CMOS 80-TQFP
產(chǎn)品培訓(xùn)模塊： Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
標(biāo)準(zhǔn)包裝： 1
分辨率（位）： 12 b
主 fclk： 300MHz
調(diào)節(jié)字寬（位）： 48 b
電源電壓： 3.14 V ~ 3.47 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 80-TQFP 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 80-TQFP-EP（12x12）
包裝： 托盤(pán)
配用： AD9852/PCBZ-ND - BOARD EVAL FOR AD9852
AD9852
Rev. E | Page 32 of 52
Table 9. Register Layout1
AD9852 Register Layout
Parallel
Address
(Hex)
Serial
Address
(Hex)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default
Value
(Hex)
00
01
0
Phase Adjust Register 1 <13:8> (Bits 15, 14 don’t care)
Phase Adjust Register 1 <7:0>
Phase 1
00
02
03
1
Phase Adjust Register 2 <13:8> (Bits 15, 14 don’t care)
Phase Adjust Register 2 <7:0>
Phase 2
00
04
05
06
07
08
09
2
Frequency Tuning Word 1 <47:40>
Frequency Tuning Word 1 <39:32>
Frequency Tuning Word 1 <31:24>
Frequency Tuning Word 1 <23:16>
Frequency Tuning Word 1 <15:8>
Frequency Tuning Word 1 <7:0>
Frequency 1
00
0A
0B
0C
0D
0E
0F
3
Frequency Tuning Word 2 <47:40>
Frequency Tuning Word 2 <39:32>
Frequency Tuning Word 2 <31:24>
Frequency Tuning Word 2 <23:16>
Frequency Tuning Word 2 <15:8>
Frequency Tuning Word 2 <7:0>
Frequency 2
00
10
11
12
13
14
15
Delta frequency word <47:40>
Delta frequency word <39:32>
Delta frequency word <31:24>
Delta frequency word <23:16>
Delta frequency word <15:8>
Delta frequency word <7:0>
00
16
17
18
19
5
Update clock <31:24>
Update clock <23:16>
Update clock <15:8>
Update clock <7:0>
00
1A
1B
1C
6
Ramp rate clock <19:16> (Bits 23, 22, 21, 20, don’t care)
Ramp rate clock <15:8>
Ramp rate clock <7:0>
00
1D
7
Don’t care
CR [31]
Don’t care
Don’t
care
Comp
PD
Reserved,
always
low
Control
DAC PD
DIG PD
10
1E
Don’t care
PLL range
Bypass
PLL
Ref
Mult 4
Ref
Mult 3
Ref Mult 2
Ref
Mult 1
Ref Mult 0
64
1F
CLR ACC1
CLR ACC2
Triangle
Don’t
care
Mode 2
Mode 1
Mode 0
Int/Ext
update clock
01
20
Don’t care
Bypass inv
sinc
OSK EN
OSK INT
Don’t care
LSB first
SDO active
CR [0]
20
21
22
8
Output shaped keying multiplier <11:8> (Bits 15, 14, 13, 12 don’t care)
Output shaped keying multiplier <7:0>
00
23
24
9
Don’t care
00
25
A
Output shaped keying ramp rate <7:0>
80
26
27
B
Control DAC <11:8> (Bits 15, 14, 13, 12 don’t care)
Control DAC <7:0> (Data is required to be in twos complement format)
00
1 The shaded sections comprise the control register.
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