V
參數(shù)資料
型號(hào)： AD9852/PCBZ
廠商： Analog Devices Inc
文件頁數(shù)： 51/52頁
文件大小： 0K
描述： BOARD EVAL FOR AD9852
設(shè)計(jì)資源： AD9852 Eval Brd BOM
AD9852 Schematic
標(biāo)準(zhǔn)包裝： 1
系列： AgileRF™
類型： 合成器
適用于相關(guān)產(chǎn)品： AD9852
相關(guān)產(chǎn)品： AD9852ASVZ-ND - IC DDS SYNTHESIZER CMOS 80-TQFP
AD9852ASTZ-ND - IC DDS SYNTHESIZER CMOS 80-LQFP
AD9852
Rev. E | Page 8 of 52
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Rating
Maximum Junction Temperature
150°C
VS
4 V
Digital Inputs
0.7 V to +VS
Digital Output Current
5 mA
Storage Temperature
65°C to +150°C
Operating Temperature
40°C to +85°C
Lead Temperature (Soldering, 10 sec)
300°C
Maximum Clock Frequency (ASVZ)
300 MHz
Maximum Clock Frequency (ASTZ)
200 MHz
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
The heat sink of the AD9852ASVZ 80-lead TQFP package must
be soldered to the PCB.
Table 3.
Thermal Characteristic
TQFP
LQFP
θJA (0 m/sec airflow)1, 2, 3
16.2°C/W
38°C/W
θJMA (1.0 m/sec airflow)2, 3, 4, 5
13.7°C/W
θJMA (2.5 m/sec airflow)2, 3, 4, 5
12.8°C/W
Ψ
JT
0.3°C/W
θJC6, 7
2.0°C/W
1 Per JEDEC JESD51-2 (heat sink soldered to PCB).
2 2S2P JEDEC test board.
3 Values of
θ
JA
are provided for package comparison and PCB design
considerations.
4 Per JEDEC JESD51-6 (heat sink soldered to PCB).
5 Airflow increases heat dissipation, effectively reducing θJA. Furthermore, the
more metal that is directly in contact with the package leads from metal
traces through holes, ground, and power planes, the more θJA is reduced.
6 Per MIL-Std 883, Method 1012.1.
7 Values of
θ
JC
are provided for package comparison and PCB design
considerations when an external heat sink is required.
To determine the junction temperature on the application PCB
use the following equation:
TJ = Tcase + (ΨJT × PD)
where:
TJ is the junction temperature expressed in degrees Celsius.
Tcase is the case temperature expressed in degrees Celsius, as
measured by the user at the top center of the package.
Ψ
JT
= 0.3°C/W.
PD is the power dissipation (PD); see the Power Dissipation and
Thermal Considerations section for the method to calculate PD.
EXPLANATION OF TEST LEVELS
Table 4.
Test Level
Description
I
100% production tested.
III
Sample tested only.
IV
Parameter is guaranteed by design and
characterization testing.
V
Parameter is a typical value only.
VI
Devices are 100% production tested at 25°C and
guaranteed by design and characterization testing
for industrial operating temperature range.
ESD CAUTION
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