參數(shù)資料
型號： AD9849KST
廠商： ANALOG DEVICES INC
元件分類： 消費家電
英文描述： CCD Signal Processors with Integrated Timing Driver
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP48
封裝： PLASTIC, LQFP-48
文件頁數(shù)： 8/36頁
文件大小： 347K
代理商： AD9849KST
REV. 0
AD9848/AD9849
–8–
36
35
34
33
32
31
30
29
28
27
26
25
13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
5
6
7
8
9
10
11
12
48 47 46 45 44
39 38 37
43 42 41 40
PIN 1
(TOP VIEW
SL
REFT
REFB
CMLEVEL
AVSS3
AVDD3
BYP3
CCDIN
BYP2
BYP1
(LSB) D0
D1
D2
D3
D4
NC = NO CONNECT
DVSS3
DVDD3
D5
D6
D7
D8
AVDD2
AVSS2
AD9848
N
N
D
D
H
V
P
H
C
C
S
S
H
H
D
D
H
H
D
R
D
A
C
A
(MSB) D9
36
35
34
33
32
31
30
29
28
27
26
25
13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
5
6
7
8
9
10
11
12
48 47 46 45 44
39 38 37
43 42 41 40
PIN 1
(TOP VIEW
SL
REFT
REFB
CMLEVEL
AVSS3
AVDD3
BYP3
CCDIN
BYP2
BYP1
D2
D3
D4
D5
D6
DVSS3
DVDD3
AVDD2
AVSS2
AD9849
D7
D8
D9
D10
D
D
D
D
H
V
P
H
C
C
S
S
H
H
D
D
H
H
D
R
D
A
C
A
(MSB) D11
PIN FUNCTION DESCRIPTIONS
Pin
Mnemonic
Type
Description
1–5
1–5
6
7
8–12
8–12
13, 14
15
16
17, 18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47, 48
47, 48
D0–D4
D2–D6
DVSS3
DVDD3
D5–D9
D7–D11
H1, H2
DVSS1
DVDD1
H3, H4
DVSS2
RG
DVDD2
AVSS1
CLI
AVDD1
AVSS2
AVDD2
BYP1
BYP2
CCDIN
BYP3
AVDD3
AVSS3
CMLEVEL
REFB
REFT
SL
SDI
SCK
CLPOB
CLPDM
HBLK
PBLK
VD
HD
DVSS4
DVDD4
NC
D0, D1
DO
DO
P
P
DO
DO
DO
P
P
DO
P
DO
P
P
DI
P
P
P
AO
AO
AI
AO
P
P
AO
AO
AO
DI
DI
DI
DI
DI
DI
DI
DI
DI
P
P
NC
DO
Data Outputs AD9848 Only
Data Outputs AD9849 Only
Digital Ground 3 – Data Outputs
Digital Supply 3 – Data Outputs
Data Outputs (D9 is MSB) AD9848 Only
Data Outputs (D9 is MSB) AD9849 Only
Horizontal Clocks (to CCD)
Digital Ground 1 – H Drivers
Digital Supply 1 – H Drivers
Horizontal Clocks (to CCD)
Digital Ground 1 – H Drivers
Reset Gate Clock (to CCD)
Digital Supply 2 – RG Driver
Analog Ground 1
Master Clock Input
Analog Supply 1
Analog Ground 2
Analog Supply 2
Bypass Pin (0.1
μ
F to AVSS)
Bypass Pin (0.1
μ
F to AVSS)
Analog Input for CCD Signal
Bypass Pin (0.1
μ
F to AVSS)
Analog Supply 3
Analog Ground 3
Internal Bias Level Decoupling (0.1
μ
F to AVSS)
Reference Bottom Decoupling (1.0
μ
F to AVSS)
Reference Top Decoupling (1.0
μ
F to AVSS)
3-Wire Serial Load (from
μ
P)
3-Wire Serial Data Input (from
μ
P)
3-Wire Serial Clock (from
μ
P)
Optical Black Clamp Pulse
Dummy Black Clamp Pulse
HCLK Blanking Pulse
Preblanking Pulse
Vertical Sync Pulse
Horizontal Sync Pulse
Digital Ground 4 – VD, HD, CLPOB, CLPDM, HBLK, PBLK, SCK, SL, SDATA
Digital Supply 4 – VD, HD, CLPOB, CLPDM, HBLK, PBLK, CK, SL, SDATA
Internally Not Connected AD9848 Only
Data Output (D0 is LSB) AD9849 Only
NOTE
Type: AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output, P = Power
PIN CONFIGURATION
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