參數(shù)資料
型號(hào)： AD9849KST
廠商： ANALOG DEVICES INC
元件分類： 消費(fèi)家電
英文描述： CCD Signal Processors with Integrated Timing Driver
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP48
封裝： PLASTIC, LQFP-48
文件頁(yè)數(shù)： 32/36頁(yè)
文件大?。?/td> 347K
代理商： AD9849KST
REV. 0
AD9848/AD9849
–32–
Driving the CLI Input
The AD9848/AD9849’s master clock input (CLI) may be
used in two different configurations, depending on the appli-
cation. Figure 23a shows a typical dc-coupled input from the
master clock source. When the dc-coupled technique is used,
the master clock signal should be at standard 3 V CMOS
logic levels. As shown in Figure 23b, a 1000 pF ac-coupling
capacitor may be used between the clock source and the CLI
input. In this configuration, the CLI input will self-bias to
the proper dc voltage level of approximately 1.4 V. When the
ac-coupled technique is used, the master clock signal can be
as low as
±
500 mV in amplitude.
17
CCD IMAGER
SIGNAL
OUT
18
13
14
20
29
H2
RG
H3
H4
H1
H2
H1
RG
AD9848/AD9849
CCDIN
Figure 22a. CCD Connections (2 H-Clock)
CCD IMAGER
SIGNAL
OUT
13
14
20
29
RG
H3
H4
H2
H1
RG
AD9848/AD9849
CCDIN
H2
H1
17
18
H1
H2
Figure 22b. CCD Connections (4 H-Clock)
CLI
23
MASTER CLOCK
AD9848/AD9849
ASIC
Figure 23a. CLI Connection, DC-Coupled
CLI
23
MASTER CLOCK
AD9848/AD9849
ASIC
LPF
1nF
Figure 23b. CLI Connection, AC-Coupled
Internal Mode Circuit Configuration
The AD9848/AD9849 may be used in Internal Mode using
the circuit configuration of Figure 24. Internal Mode uses the
same circuit as Figure 21, except that the horizontal pulses
(CLPOB, CLPDM, PBLK, and HBLK) are internally gener-
ated in the AD9848/AD9849. These pins may be grounded when
Internal Mode is used. Only the HD and VD signals are required
from the ASIC.
HD/VD
INPUTS
2
44
39
43
42
41
40
H
V
P
H
C
C
AD9848/AD9849
Figure 24. Internal Mode Circuit Configuration
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