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參數(shù)資料
| 型號： | AD9849KST |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | CCD Signal Processors with Integrated Timing Driver |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| 封裝： | PLASTIC, LQFP-48 |
| 文件頁數(shù)： | 13/36頁 |
| 文件大?。?/td> | 347K |
| 代理商： | AD9849KST |
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REV. 0
AD9848/AD9849
–13–
Bit
Content
Default
Value
Address
Width
Register Name
Register Description
AFE Registers
# Bits
56
00
01
02
03
04
05
06
07
08
09
0A
[5:0]
[1:0]
[5:0]
[3:0]
[5:0]
[1:0]
[5:0]
[5:0]
[5:0]
[5:0]
[5:0]
6
2
6
4
6
2
6
6
6
6
6
00
00
16
02
00
02
00
00
00
00
00
oprmode[5:0]
oprmode[7:6]
ccdgain[5:0]
ccdgain[9:6]
refblack[5:0]
refblack[7:6]
ctlmode
pxga gain0
pxga gain1
pxga gain2
pxga gain3
AFE Operation Mode (See AFE Register Breakdown)
VGA Gain
Black Clamp Level
Control Mode (See AFE Register Breakdown)
PxGA Color 0 Gain
PxGA Color 1 Gain
PxGA Color 2 Gain
PxGA Color 3 Gain
Miscellaneous/Extra
# Bits
26
16
17
18
19
1A
1B
1C
[0]
[5:0]
[5:0]
[0]
[0]
[5:0]
[0]
1
6
6
1
1
6
1
00
00
00
00
00
00
00
out_cont
update[5:0]
update[11:6]
preventupdate
readback
doutphase
disablerestore
Output Control (0 = Make All Outputs DC Inactive)
Serial Data Update Control (Sets the line within the field
for serial data update to occur.)
Prevent the Update of the “VD/HD Updated” Registers
Serial Interface Readback Enable
DOUT Phase Control
Disable CCDIN DC Restore Circuit During PBLK
(1 = Disable)
VD/HD Active Polarity (0 = Low Active, 1 = High Active)
Internal Field Pulse Value (0 = Next Field Odd,
1 = Next Field Even)
Re-Sync hblk to h1 Clock
Addresses 20 to 25 Reserved for Internal Test Modes
TG Core Reset_Bar (0 = Hold TG Core in Reset,
1 = Resume Normal Operation)
1D
1E
[0]
[0]
1
1
00
01
vdhdpol
fieldval
1F
20
26
[0]
1
00
hblkretime
internal test mode
tgcore_rstb
[0]
1
00
Notes about Accessing a Double-Wide Register
There are many double-wide registers in the AD9848/AD9849, for example: oprmode, clpdmtog1_0, clpdmscp3, etc. These regis-
ters are configured into two consecutive 6-bit registers with the least significant six bits located in the lower of the two addresses and
the remaining most significant bits located in the higher of the two addresses. For example, the 6 LSBs of the clpdmscp3 regis-
ter, clpdmscp3[5:0], are located at address 0x81. The most significant six bits of the clpdmscp3 register, clpdmscp3[11:6], are
located at address 0x82. The following rules must be followed when accessing double-wide registers:
1. When accessing a double-wide register, BOTH addresses must be written to.
2. The lower of the two consecutive addresses for the double-wide register must be written to first. In the example of the clpdmscp3
register, the contents of address 0x81 must be written first followed by the contents of address 0x82. The register will be updated
after the completion of the write to register 0x82, either at the next SL rising edge or next VD/HD falling edge.
3. A single write to the lower of the two consecutive addresses of a double-wide register that is not followed by a write to the higher
address of the registers, is not permitted. This will not update the register.
4. A single write to the higher of the two consecutive addresses of a double-wide register that is not preceded by a write to the lower
of the two address, is not permitted. Although the write to the higher address will update the full double-wide register, the lower
six bits of the register will be written with an indeterminate value if the lower address was not written first.
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