參數(shù)資料
型號(hào)： AD9847AKST
廠商： ANALOG DEVICES INC
元件分類： 消費(fèi)家電
英文描述： 10-Bit 40 MSPS CCD Signal Processor with Integrated Timing Driver
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP48
封裝： 1.40 MM HEIGHT, PLASTIC, MS-026BBC, LQFP-48
文件頁(yè)數(shù)： 17/28頁(yè)
文件大小： 428K
代理商： AD9847AKST
REV. A
AD9847
–17–
H-Driver and RG Outputs
In addition to the programmable timing positions, the AD9847
features on-chip output drivers for the RG and H1–H4 outputs.
These drivers are powerful enough to directly drive the CCD
inputs. The H-driver current can be adjusted for optimum rise/fall
time into a particular load by using the DRV registers. The RG
drive current is adjustable using the RGDRV register. Each 3-bit
DRV register is adjustable in 3.5 mA increments, with the mini-
mum setting of 0 equal to OFF or three-state and the maximum
setting of 7 equal to 24.5 mA.
As shown in Figure 7, the H2/H4 outputs are inverses of H1/H3.
The internal propagation delay resulting from the signal inversion
is less than 1 ns, which is significantly less than the typical rise
time driving the CCD load. This results in a H1/H2 crossover
voltage at approximately 50% of the output swing. The crossover
voltage is not programmable.
P[0]
PIXEL
PERIOD
RG
H1/H3
RGf[12]
P[48] = P[0]
Hf[24]
SHP[28]
CCD SIGNAL
P[24]
P[12]
P[36]
Hr[0]
RGr[0]
SHD[48]
NOTES
1. ALL SIGNAL EDGES ARE FULLY PROGRAMMABLE TO ANY OF THE 48 POSITIONS WITHIN ONE PIXEL PERIOD.
2. DEFAULT POSITIONS FOR EACH SIGNAL ARE SHOWN ABOVE.
POSITION
t
S1
Figure 6. High Speed Clock Default and Programmable Locations
H2/H4
H1/H3
H1/H3
H2/H4
t
RISE
t
PD
<<
t
RISE
FIXED CROSSOVER VOLTAGE
t
PD
Figure 7. H-Clock Inverse Phase Relationship
Digital Data Outputs
The AD9847 data output phase is programmable using the
DOUTPHASE register. Any edge from 0 to 47 may be programmed,
as shown in Figure 8.
NOTES
1. DIGITAL OUTPUT DATA (DOUT) PHASE IS ADJUSTABLE WITH RESPECT TO THE PIXEL PERIOD.
2. WITHIN 1 CLOCK PERIOD, THE DATA TRANSITION CAN BE PROGRAMMED TO ANY OF THE 48 LOCATIONS.
P[0]
P[48] = P[0]
CLI
1 PIXEL PERIOD
P[12]
P[24]
P[36]
DOUT
t
OD
Figure 8. Digital Output Phase Adjustment
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