參數(shù)資料
型號: AD9847AKST
廠商: ANALOG DEVICES INC
元件分類: 消費家電
英文描述: 10-Bit 40 MSPS CCD Signal Processor with Integrated Timing Driver
中文描述: SPECIALTY CONSUMER CIRCUIT, PQFP48
封裝: 1.40 MM HEIGHT, PLASTIC, MS-026BBC, LQFP-48
文件頁數(shù): 16/28頁
文件大?。?/td> 428K
代理商: AD9847AKST
REV. A
AD9847
–16–
High Speed Clock Programmability
Figure 5 shows how the high speed clocks RG, H1–H4, SHP,
and SHD are generated. The RG pulse has programmable rising
and falling edges and may be inverted using the polarity control.
The horizontal clocks H1 and H3 have programmable rising and
falling edges and polarity control. The H2 and H4 clocks are
always inverses of H1 and H3, respectively. Table II summarizes
the high speed timing registers and their parameters.
The edge location registers are 6 bits wide, but there are only 48
valid edge locations available. Therefore, the register values are
mapped into four quadrants, with each quadrant containing 12edge
locations. Table III shows the correct register values for the
corresponding edge locations. Figure 6 shows the range and
default locations of the high speed clock signals.
Table II. H1–H4, RG, SHP, SHD Timing Parameters
Register Name
Length
Range
Description
POL
POSLOC
1b
6b
High/Low
0–47 Edge Location
Polarity Control for H1, H3, and RG (0 = No Inversion, 1 = Inversion)
Positive Edge Location for H1, H3, and RG
Sample Location for SHP, SHD
Negative Edge Location for H1, H3, and RG
Drive Current for H1–H4 and RG Outputs (3.5 mA per Step)
NEGLOC
DRV
6b
3b
0–47 Edge Location
0–7 Current Steps
Table III.
Precision Timing
Edge Locations
Quadrant
Edge Location (Decimal)
Register Value (Decimal)
Register Value (Binary)
I
II
III
IV
0 to 11
12 to 23
24 to 35
36 to 47
0 to 11
16 to 27
32 to 43
48 to 59
000000 to 001011
010000 to 011011
100000 to 101011
110000 to 111011
H1/H3
H2/H4
CCD SIGNAL
RG
(1)
(2)
(3)
(4)
(5)
(6)
NOTES
PROGRAMMABLE CLOCK POSITIONS:
(1) RG RISING EDGE AND (2) FALLING EDGE
(3) SHP AND (4) SHD SAMPLE LOCATION
(5) H1/H3 RISING EDGE POSITION AND (6) FALLING EDGE POSITION (H2/H4 ARE INVERSE OF H1/H3)
Figure 5. High Speed Clock Programmable Locations
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