參數(shù)資料
型號: AD9840AJSTZRL
廠商: Analog Devices Inc
文件頁數(shù): 2/16頁
文件大小: 0K
描述: IC CCD SIGNAL PROC 10BIT 48LQFP
標(biāo)準(zhǔn)包裝: 2,000
類型: CCD 信號處理器,10 位
輸入類型: 邏輯
輸出類型: 邏輯
接口: 3 線串口
安裝類型: 表面貼裝
封裝/外殼: 48-LQFP
供應(yīng)商設(shè)備封裝: 48-LQFP(7x7)
包裝: 帶卷 (TR)
AD9840A
–10–
REV. 0
Table II. Operation Register Contents (Default Value x000)
Optical Black Clamp
Reset
Power-Down Modes
Channel Selection
D10
D9
D8
D7
D6
D5
D4
D3 D2
D1 D0
0
*
0
*
0
*
1
**
0
*
0
Enable Clamping
0 Normal
0
0 Normal Power
0
CCD-Mode
1
Disable Clamping
1 Reset all
0
1 Fast Recovery
0
1
AUX1-Mode
Registers
1
0 Standby
1
0
AUX2-Mode
to Default
1
1 Total Power-Down 1
1
Test Only
*Must be set to zero. **Set to one.
Table III. VGA Gain Register Contents (Default Value x096)
MSB
LSB
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Gain (dB)
X
0
010111112.0
1
11111110
35.965
1
11111111
36.0
Table IV. Clamp Level Register Contents (Default Value x080)
MSB
LSB
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Clamp Level (LSB)
X
0000
0
000
0
0000
0
001
0.25
0000
0
010
0.5
11111110
63.5
11111111
63.75
Table V. Control Register Contents (Default Value x000)
Data Out
DATACLK
CLP/PBLK
SHP/SHD
CDS Gain
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
0 Enable
0
*
0
*
0 Rising Edge Trigger
0 Active Low
0 Disabled
** 0*
0
*
0
*
1 Three-State
1 Falling Edge Trigger
1 Active High
1 Enabled
*Must be set to zero.
**When D3 = 0 (CDS Gain Disabled), the CDS Gain Register is fixed at 4 dB (code 63 dec).
Table VI. CDS Gain Register Contents (Default Value x000)
MSB
LSB
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Gain (dB)
*
X
000000
+4.3
011110
+10.0
100000–2.0
111111+4.0
*Control Register Bit D3 must be set high for the CDS Gain Register to be used.
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