tID
參數(shù)資料
型號: AD9840AJSTZRL
廠商: Analog Devices Inc
文件頁數(shù): 15/16頁
文件大小: 0K
描述: IC CCD SIGNAL PROC 10BIT 48LQFP
標(biāo)準(zhǔn)包裝: 2,000
類型: CCD 信號處理器,10 位
輸入類型: 邏輯
輸出類型: 邏輯
接口: 3 線串口
安裝類型: 表面貼裝
封裝/外殼: 48-LQFP
供應(yīng)商設(shè)備封裝: 48-LQFP(7x7)
包裝: 帶卷 (TR)
AD9840A
–8–
REV. 0
CCD-MODE AND AUX-MODE TIMING
N–10
N–9
N–8
N–1
N
N+1
N+2
N+9
N+10
tID
tS1
tS2
tCP
tINH
tOD
tH
NOTES:
1. RECOMMENDED PLACEMENT FOR DATACLK RISING EDGE IS BETWEEN THE SHD RISING EDGE AND NEXT SHP FALLING EDGE.
2. CCD SIGNAL IS SAMPLED AT SHP AND SHD RISING EDGES.
SHP
SHD
DATACLK
OUTPUT
DATA
CCD
SIGNAL
Figure 5. CCD-Mode Timing
CCD
SIGNAL
EFFECTIVE PIXELS
CLPOB
CLPDM
OPTICAL BLACK PIXELS
HORIZONTAL
BLANKING
DUMMY PIXELS
EFFECTIVE PIXELS
PBLK
NOTES:
1. CLPOB AND CLPDM WILL OVERWRITE PBLK. PBLK WILL NOT AFFECT CLAMP OPERATION IF OVERLAPPING CLPDM AND/OR CLPOB.
2. PBLK SIGNAL IS OPTIONAL.
3. DIGITAL OUTPUT DATA WILL BE ALL ZEROS DURING PBLK. OUTPUT DATA LATENCY IS 9 DATACLK CYCLES.
OUTPUT
DATA
EFFECTIVE PIXEL DATA
OB PIXEL DATA
DUMMY BLACK
EFFECTIVE DATA
Figure 6. Typical CCD-Mode Line Clamp Timing
DATACLK
OUTPUT
DATA
VIDEO
SIGNAL
N
N+1
N+2
N+8
N+9
N–10
N–9N–8N–1N
tID
tCP
tOD
tH
Figure 7. AUX-Mode Timing
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