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參數(shù)資料
| 型號： | AD9840AJSTZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 12/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CCD SIGNAL PROC 10BIT 48LQFP |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 類型： | CCD 信號處理器，10 位 |
| 輸入類型： | 邏輯 |
| 輸出類型： | 邏輯 |
| 接口： | 3 線串口 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 帶卷 (TR) |
AD9840A
–5–
REV. 0
TIMING SPECIFICATIONS
Parameter
Symbol
Min
Typ
Max
Unit
SAMPLE CLOCKS
DATACLK, SHP, SHD Clock Period
tCP
25
ns
DATACLK Hi/Low Pulsewidth
tADC
10
12.5
ns
SHP Pulsewidth
tSHP
56
ns
SHD Pulsewidth
tSHD
56
ns
CLPDM Pulsewidth
tCDM
4
10
Pixels
CLPOB Pulsewidth
1
tCOB
2
20
Pixels
SHP Rising Edge to SHD Falling Edge
tS1
06
ns
SHP Rising Edge to SHD Rising Edge
tS2
10
12.5
ns
Internal Clock Delay
tID
3.0
ns
Inhibited Clock Period
tINH
10
ns
DATA OUTPUTS
Output Delay
tOD
14.5
16
ns
Output Hold Time
tH
7.0
7.6
ns
Pipeline Delay
9
Cycles
SERIAL INTERFACE
Maximum SCK Frequency
fSCLK
10
MHz
SL to SCK Setup Time
tLS
10
ns
SCK to SL Hold Time
tLH
10
ns
SDATA Valid to SCK Rising Edge Setup
tDS
10
ns
SCK Falling Edge to SDATA Valid Hold
tDH
10
ns
SCK Falling Edge to SDATA Valid Read
tDV
10
ns
NOTES
1Minimum CLPOB pulsewidth is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp performance.
Specifications subject to change without notice.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9840A features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
(CL = 20 pF, fSAMP = 40 MHz, CCD-Mode Timing in Figures 5 and 6, AUX-Mode Timing in Figure 7.
Serial Timing in Figures 8–10.)
ABSOLUTE MAXIMUM RATINGS
With
Respect
Parameter
To
Min
Max
Unit
AVDD1, AVDD2
AVSS
–0.3
+3.9
V
DVDD1, DVDD2
DVSS
–0.3
+3.9
V
DRVDD
DRVSS
–0.3
+3.9
V
Digital Outputs
DRVSS
–0.3
DRVDD + 0.3
V
SHP, SHD, DATACLK
DVSS
–0.3
DVDD + 0.3
V
CLPOB, CLPDM, PBLK
DVSS
–0.3
DVDD + 0.3
V
SCK, SL, SDATA
DVSS
–0.3
DVDD + 0.3
V
VRT, VRB, CMLEVEL
AVSS
–0.3
AVDD + 0.3
V
BYP1-4, CCDIN
AVSS
–0.3
AVDD + 0.3
V
Junction Temperature
150
°C
Lead Temperature
300
°C
(10 sec)
ORDERING GUIDE
Temperature
Package
Model
Range
Description
Option
AD9840AJST –20
°C to +85°C
Thin Plastic
ST-48
Quad Flatpack
(LQFP)
THERMAL CHARACTERISTICS
Thermal Resistance
48-Lead LQFP Package
θJA = 92°C
WARNING!
ESD SENSITIVE DEVICE
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| AD9840-EB | 制造商:Analog Devices 功能描述:10 BIT 40HZ ANALOG FRONT END NO PXGA - Bulk |
| AD9840JST | 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel |
| AD9840JSTRL | 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel |
| AD9841A | 制造商:AD 制造商全稱:Analog Devices 功能描述:Complete 20 MSPS CCD Signal Processors |
| AD9841AJST | 制造商:Analog Devices 功能描述:AFE Video 1ADC 10-Bit 3.3V 48-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:10 BIT 20 MHZ ANALOG FRONT END - Tape and Reel |
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