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參數(shù)資料
| 型號(hào)： | AD9814JRRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 6/15頁 |
| 文件大小： | 0K |
| 描述： | IC CCD SIGNAL PROC 14BIT 28-SOIC |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類型： | CCD 信號(hào)處理器，14 位 |
| 輸入類型： | 邏輯 |
| 輸出類型： | 邏輯 |
| 接口： | 3 線串口 |
| 電流 - 電源： | 80mA |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SOIC W |
| 包裝： | 帶卷 (TR) |
REV. 0
AD9814
–14–
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
AD9814
CDSCLK1
AVDD
CDSCLK2
ADCCLK
OEB
DRVDD
DRVSS
D7 (MSB)
D6
D5
D4
D3
D2
D1
D0 (LSB)
AVSS
VINR
OFFSET
VING
CML
VINB
CAPT
CAPB
AVSS
AVDD
SLOAD
SCLK
SDATA
3
CLOCK INPUTS
8
DATA OUTPUTS
0.1 F
3
SERIAL INTERFACE
0.1 F
+5V/3V
+5V
0.1 F
RED INPUT
GREEN INPUT
BLUE INPUT
0.1 F
1.0 F
10 F
0.1 F
+
0.1 F
+5V
0.1 F
Figure 15. Recommended Circuit Configuration, 3-Channel CDS Mode
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
AD9814
CDSCLK1
AVDD
CDSCLK2
ADCCLK
OEB
DRVDD
DRVSS
D7 (MSB)
D6
D5
D4
D3
D2
D1
D0 (LSB)
AVSS
VINR
OFFSET
VING
CML
VINB
CAPT
CAPB
AVSS
AVDD
SLOAD
SCLK
SDATA
3
CLOCK INPUTS
8
DATA OUTPUTS
0.1 F
3
SERIAL INTERFACE
0.1 F
+5V/3V
+5V
0.1 F
RED INPUT
GREEN INPUT
BLUE INPUT
0.1 F
10 F
0.1 F
+
0.1 F
+5V
0.1 F
Figure 16. Recommended Circuit Configuration, 3-Channel SHA Mode
(Analog Inputs Sampled with Respect to Ground)
APPLICATIONS INFORMATION
Circuit and Layout Recommendations
The recommended circuit configuration for 3-Channel CDS
mode operation is shown in Figure 15. The recommended input
coupling capacitor value is 0.1
F (see Circuit Operation section
for more details). A single ground plane is recommended for the
AD9814. A separate power supply may be used for DRVDD,
the digital driver supply, but this supply pin should still be
decoupled to the same ground plane as the rest of the AD9814.
The loading of the digital outputs should be minimized, either
by using short traces to the digital ASIC, or by using external
digital buffers. To minimize the effect of digital transients during
major output code transitions, the falling edge of CDSCLK2
should occur coincident with or before the rising edge of
ADCCLK (see Figures 1 through 4 for timing). All 0.1
F
decoupling capacitors should be located as close as possible to
the AD9814 pins. When operating in single channel mode, the
unused analog inputs should be grounded.
Figure 16 shows the recommended circuit configuration for 3-
Channel SHA mode. All of the above considerations also apply
for this configuration, except that the analog input signals are
directly connected to the AD9814 without the use of coupling
capacitors. The analog input signals must already be dc-biased
between 0 V and 4 V (see the Circuit Operation section for
more details).
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參數(shù)描述 |
|---|---|
| AD9814KR | 制造商:Analog Devices 功能描述:AFE Video 1ADC 14-Bit 5V 28-Pin SOIC W 制造商:Analog Devices 功能描述:14 BIT 6 MSPS SCANNER ANALOG FRONT END - Rail/Tube 制造商:Rochester Electronics LLC 功能描述:14 BIT 6 MSPS SCANNER ANALOG FRONT END - Bulk |
| AD9814KRRL | 制造商:Analog Devices 功能描述:AFE Video 1ADC 14-Bit 5V 28-Pin SOIC W 制造商:Analog Devices 功能描述:14 BIT 6 MSPS SCANNER ANALOG FRONT END - Tape and Reel 制造商:Rochester Electronics LLC 功能描述:14 BIT 6 MSPS SCANNER ANALOG FRONT END - Bulk |
| AD9814S | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit CCD/CIS Signal Processor |
| AD9816 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Complete 12-Bit 6 MSPS CCD/CIS Signal Processor |
| AD9816-EB | 制造商:Analog Devices 功能描述:12-BIT 4MSPS CCD/CIS SIGNAL PROCESSOR - Bulk |
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