參數(shù)資料
型號(hào): AD9814JRRL
廠商: Analog Devices Inc
文件頁(yè)數(shù): 2/15頁(yè)
文件大?。?/td> 0K
描述: IC CCD SIGNAL PROC 14BIT 28-SOIC
標(biāo)準(zhǔn)包裝: 1,000
類(lèi)型: CCD 信號(hào)處理器,14 位
輸入類(lèi)型: 邏輯
輸出類(lèi)型: 邏輯
接口: 3 線串口
電流 - 電源: 80mA
安裝類(lèi)型: 表面貼裝
封裝/外殼: 28-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 28-SOIC W
包裝: 帶卷 (TR)
REV. 0
AD9814
–10–
INTERNAL REGISTER DESCRIPTIONS
Table I. Internal Register Map
Register
Address
Data Bits
Name
A2
A1
A0
D8
D7
D6
D5
D4
D3
D2
D1
D0
Configuration
0
Input Rng
VREF
3Ch/1Ch
CDS On
Clamp
Pwr Dn
0
MUX
0
1
0
RGB/BGR
Red
Green
Blue
0
Red PGA
0
1
0
MSB
LSB
Green PGA
0
1
0
MSB
LSB
Blue PGA
1
0
MSB
LSB
Red Offset
1
0
1
MSB
LSB
Green Offset
1
0
MSB
LSB
Blue Offset
1
MSB
LSB
Configuration Register
The Configuration Register controls the AD9814’s operating mode and bias levels. Bits D8, D1 and D0 should always be set low. Bit
D7 sets the full-scale voltage range of the AD9814’s A/D converter to either 4 V (high) or 2 V (low). Bit D6 controls the internal
voltage reference. If the AD9814’s internal voltage reference is used, this bit is set high. Setting Bit D6 low will disable the internal
voltage reference, allowing an external voltage reference to be used. Bit D5 will configure the AD9814 for either the 3-Channel (high)
or 1-Channel (low) mode of operation. Setting Bit D4 high will enable the CDS mode of operation, and setting this bit low will en-
able the SHA mode of operation. Bit D3 sets the dc bias level of the AD9814’s input clamp. This bit should always be set high for
the 4 V clamp bias, unless a CCD with a reset feedthrough transient exceeding 2 V is used. If the 3 V clamp bias level is used, the
peak-to-peak input signal range to the AD9814 is reduced to 3 V maximum. Bit D2 controls the power-down mode. Setting Bit D2
high will place the AD9814 into a very low power “sleep” mode. All register contents are retained while the AD9814 is in the pow-
ered-down state.
Table II. Configuration Register Settings
D8
D7
D6
D5
D4
D3
D2
D1
D0
Set
Input Range
Internal VREF
# of Channels
CDS Operation
Input Clamp Bias
Power-Down
Set
to
1 = 4 V*
1 = Enabled*
1 = 3-Ch Mode*
1 = CDS Mode*
1 = 4 V*
1 = On
to
0
0 = 2 V
0 = Disabled
0 = 1-Ch Mode
0 = SHA Mode
0 = 3 V
0 = Off (Normal)* 00
*Power-on default value.
MUX Register
The MUX Register controls the sampling channel order in the AD9814. Bits D8, D3, D2, D1, and D0 should always be set low. Bit
D7 is used when operating in 3-Channel Mode. Setting Bit D7 high will sequence the MUX to sample the red channel first, then the
green channel and then the blue channel. When in this mode, the CDSCLK2 pulse always resets the MUX to sample the red channel
first (see Timing Figure 1). When Bit D7 is set low, the channel order is reversed to blue first, green second and red third. The
CDSCLK2 pulse will always reset the MUX to sample the blue channel first. Bits D6, D5, and D4 are used when operating in
1-Channel Mode. Bit D6 is set high to sample the red channel. Bit D5 is set high to sample the green channel. Bit D4 is set high to
sample the blue channel. The MUX will remain stationary during 1-Channel Mode.
Table III. MUX Register Settings
D8
D7
D6
D5
D4
D3
D2
D1
D0
Set
3-Channel Select
1-Channel Select
Set
to
1 = R-G-B*
1 = RED*
1 = GREEN
1 = BLUE
to
0
0 = B-G-R
0 = Off
0 = Off*
00
0
*Power-on default value.
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