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參數(shù)資料
| 型號(hào)： | AD9806KSTZRL |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 10/12頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC CCD SIGNAL PROC 10BIT 48LQFP |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 類型： | CCD 信號(hào)處理器，10 位 |
| 輸入類型： | 邏輯 |
| 輸出類型： | 邏輯 |
| 接口： | 3 線串口 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 帶卷 (TR) |
REV. 0
AD9806
–7–
TIMING SPECIFICATIONS
N
N+1
N+2
N+3
N+4
tINHIBIT
tID
tOD
tHOLD
ADCCLK RISING EDGE PLACEMENT
N–0N–9N–8N–7N–6N–5
CCD
SHP
SHD
ADCCLK
D0–D9
NOTES:
1. SHP AND SHD SHOULD BE OPTIMALLY ALIGNED WITH THE CCD SIGNAL. SAMPLES ARE TAKEN AT THE RISING EDGES.
2. ADCCLK RISING EDGE MUST OCCUR AT LEAST 15ns AFTER THE RISING EDGE OF SHP (
tINHIBIT).
3. RECOMMENDED PLACEMENT FOR ADCCLK RISING EDGE IS BETWEEN THE RISING EDGE OF SHD AND FALLING EDGE OF SHP.
4. OUTPUT LATENCY IS 9 CYCLES.
5. ACTIVE LOW CLOCK PULSE MODE IS SHOWN.
Figure 1. CCD-MODE Timing
tID
tOD
tHOLD
N
N+1
N+2
N+3
N+4
N–9N–8N–7
N+5
VIDEO
INPUT
ADCCLK
D0–D9
N–6N–5
NOTE:
EXAMPLE OF OUTPUT DATA LATCHED BY ADCCLK RISING EDGE.
Figure 2. AUX-, AUXMID-, ADC-Mode Timing
CCD
SIGNAL
CLPOB
CLPDM
PBLK
EFFECTIVE
PIXELS
OPTICAL BLACK
BLANKING
INTERVAL
DUMMY BLACK
EFFECTIVE
PIXELS
NOTES:
1. CLPOB PULSEWIDTH SHOULD BE A MINIMUM OF 10 OB PIXELS WIDE, 20 OB PIXELS ARE RECOMMENDED.
2. CLPDM PULSEWIDTH SHOULD BE AT LEAST 1 s WIDE.
3. PBLK IS NOT REQUIRED, BUT RECOMMENDED IF THE CCD SIGNAL AMPLITUDE EXCEEDS 1V p-p.
4. CLPDM OVERWRITES PBLK.
5. ACTIVE LOW CLAMP PULSE MODE IS SHOWN.
Figure 3. CCD-MODE Clamp Timing
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