tSREFCLK t" />
參數(shù)資料
型號(hào)： AD9788BSVZ
廠商： Analog Devices Inc
文件頁數(shù)： 30/64頁
文件大?。?/td> 0K
描述： IC DAC 16BIT 800MSPS 100TQFP
產(chǎn)品培訓(xùn)模塊： Data Converter Fundamentals
DAC Architectures
設(shè)計(jì)資源： Powering the AD9788 Using ADP2105 for Increased Efficiency (CN0141)
標(biāo)準(zhǔn)包裝： 1
系列： TxDAC®
位數(shù)： 16
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 2
電壓電源： 模擬和數(shù)字
功率耗散（最大）： 450mW
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 100-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝： 100-TQFP-EP（14x14）
包裝： 托盤
輸出數(shù)目和類型： 4 電流，單極；4 電流，雙極
采樣率（每秒）： 800M
產(chǎn)品目錄頁面： 785 (CN2011-ZH PDF)
AD9785/AD9787/AD9788
Rev. A | Page 36 of 64
DACCLK
REFCLK
INPUT
DATA
tSREFCLK
tHREFCLK
SYNC_I
tS_SYNC
tH_SYNC
07
09
8-
11
1
Figure 51. REFCLK 8×
OPTIMIZING THE DATA INPUT TIMING
The AD9785/AD9787/AD9788 have on-chip circuitry that
enables the user to optimize the input data timing by adjusting
the relationship between the DATACLK output and DCLK_SMP,
the internal clock that samples the input data. This optimization
is made by a sequence of SPI register read and write operations.
The timing optimization can be done under strict control of the
user, or the device can be programmed to maintain a configurable
timing margin automatically.
Figure 52 shows the circuitry that detects sample timing errors
and adjusts the data interface timing. The DCLK_SMP signal is
the internal clock used to latch the input data. Ultimately, it is
the rising edge of this signal that must be centered in the valid
sampling period of the input data. This is accomplished by
adjusting the time delay, tD, which changes the DATACLK
timing and, as a result, the arrival time of the input data with
respect to DCLK_SMP.
07
09
8
-06
1
TIMING
ERROR
IRQ
D
Q
D
CLK
DCLK_SMP
PD1[0]
DATACLK DELAY[4:0]
DATA
TIMING MARGIN[3:0]
DATACLK
TIMING
ERROR
TYPE
TIMING
ERROR
DETECTION
Δ
tD
Δ
tM
Δ
tM
Figure 52. Timing Error Detection and Optimization Circuitry
The error detection circuitry works by creating two sets of
sampled data (referred to as the margin test data) in addition to
the actual sampled data used in the device datapath. One set of
sampled data is latched before the actual data sampling point.
The other set of sampled data is latched after the actual data
sampling point. If the margin test data matches the actual data,
the sampling is considered valid and no error is declared. If
there is a mismatch between the actual data and the margin test
data, an error is declared.
The Data Timing Margin [3:0] variable (Register 0x02, Bits [10:7])
determines the amount of time before and after the actual data
sampling point the margin test data are latched. That is, the
Data Timing Margin [3:0] variable determines how much setup
and hold margin the interface needs for the data timing error
IRQ to remain inactive (to show error-free operation). There-
fore, the data timing error IRQ is set whenever the setup and
hold margins drop below the Data Timing Margin [3:0] value.
This does not necessarily indicate that the data latched into the
device is incorrect.
In addition to setting the data timing error IRQ, the data timing
error type bit (Register 0x09, Bit 5) is set when an error occurs.
The data timing error bit is set low to indicate a hold error and
high to indicate a setup error. Figure 53 shows a timing diagram
of the data interface and the status of the data timing error type bit.
07
09
8-
06
2
Δ
tM
Δ
tM
ACTUAL
SAMPLING
INSTANT
TIMING ERROR = 1,
DATA TIMING ERROR TYPE = 1
DATA TIMING ERROR = 1,
DATA TIMING ERROR TYPE = 0
DATA
TIMING ERROR = 0
DELAYED
DATA
SAMPLING
DELAYED
CLOCK
SAMPLING
Figure 53. Timing Diagram of Margin Test Data
Automatic Timing Optimization Mode
When the automatic timing optimization mode is enabled
(Register 0x02, Bit 3 = 1), the device continuously monitors the
timing error IRQ and timing error type bits. The DATACLK
Delay [4:0] value (Register 0x02, Bits [4:0]) increases if a setup
error is detected and decreases if a hold error is detected. The
value of the DATACLK Delay [4:0] setting currently in use can
be read back by the user.
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