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參數(shù)資料
| 型號(hào)： | AD9786BSV |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | 16-Bit, 200 MSPS/500 MSPS TxDAC+ with 2】/4】/8】 Interpolation and Signal Processing |
| 中文描述： | PARALLEL, WORD INPUT LOADING, 16-BIT DAC, PQFP80 |
| 封裝： | PLASTIC, MS-026-ADD, TQFP-80 |
| 文件頁(yè)數(shù)： | 30/60頁(yè) |
| 文件大小： | 1497K |
| 代理商： | AD9786BSV |
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AD9786
AD9786 External Sync Mode
There is one additional timing mode in which the AD9786 may
be used. In the External Sync Mode, the DATACLK is
programmed as an input, but is not used. Applying a DATACLK
input while in this mode will have no effect. The digital input
data is synchronized solely to the DACCLK input. With 1×
interpolation, this means that the data input will be latched on
every rising edge of DACCLK. The challenge is that the user has
no way of knowing exactly which edge is the latching edge
when the interpolating filters are in use. In 2
×
, 4
×
, and 8×
interpolation modes, the latching edge of DACCLK will be
either every 2
nd
, 4
th
, or 8
th
edge, respectively.
Rev. 0 | Page 30 of 60
With the 2 ns keep out window, as shown in Figure 53, there is
a strong possibility of violating setup and hold times, especially
at high speeds. It is recommended that users sense the DAC
output noise floor for setup and hold violations. If setup and
hold is violated, DCLKPOL can be switched. The effect of
switching the state of DCLKPOL is that the latching edge will
be moved by one, two, or four DACCLK cycles if the AD9786 is
in 2
×
, 4
×
, or 8× interpolation modes, respectively.
Note that in this mode, the DATAADJ bits have no effect.
0
t
S
= –300ps TYP
t
H
= 2.9ns TYP
DACCLK
IN
DATA
Figure 53. External Sync Mode with 2
×
Interpolation
DATAADJUST Synchronization
When designing the digital interface for high speed DACs, care
must be taken to ensure that the DAC input data meets setup
and hold requirements. Often, compensation must be used in
the clock delay path to the digital engine driving the DAC. The
AD9786 has the on-chip capability to vary the latching edge of
DACCLK. With the interpolation function enabled, this allows
the user the choice of multiple edges upon which to latch the
data. For instance, if the AD9786 is using 8× interpolation, the
user may latch from one of eight edges before the rising edge of
DATACLK, or seven edges after this rising edge. The specific
edge upon which data is latched is controlled by SPI Register
05h, Bits 7:4. Table 27 shows the relationship of the latching
edge of DACCLK and DATACLK with the various settings of
the DATAADJ bits.
Table 27. DATAADJ Values for Latching Edge Sync
SPI Reg 05h
Bit 7
Bit 6
Bit 5
Bit 4
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
Latching Edge wrt DATACLK
0
+1
+2
+3
+4
+5
+6
+7
–8
–7
–6
–5
–4
–3
–2
–1
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