參數(shù)資料
型號: AD9786BSV
廠商: ANALOG DEVICES INC
元件分類: DAC
英文描述: 16-Bit, 200 MSPS/500 MSPS TxDAC+ with 2】/4】/8】 Interpolation and Signal Processing
中文描述: PARALLEL, WORD INPUT LOADING, 16-BIT DAC, PQFP80
封裝: PLASTIC, MS-026-ADD, TQFP-80
文件頁數(shù): 26/60頁
文件大?。?/td> 1497K
代理商: AD9786BSV
AD9786
AD9786 CLOCK/DATA TIMING
Table 26. Data Port Synchronization
DCLKEXT
02h, Bit 3
05h, Bit 3
1
0
1
1
0
0
0
0
0
1
0
1
Rev. 0 | Page 26 of 60
MODSYNC
DCLKCRC
02h, Bit 2
X
X
0
1
0
1
Mode
DATACLK Master
Modulator Master
External Sync Mode
DATACLK Slave
Low Setup/Hold
Modulator Slave
Function
Channel data rate clock output
Modulator synchronization DATACLK output
DATACLK inactive, DACCLK synchronous with external data
DATACLK input, data rate clock, Data Recovery On
DATACLK input, input data synchronous with DATACLK
Input modulator synchronizer DATACLK input
Two-Port Data Input Mode, DATACLK Master
With the interpolation set to 1×, the DATACLK output is a
delayed and inverted version of DACCLK at the same
frequency. Note that DACCLK refers to the differential clock
inputs applied at Pins 5 and 6. As Figure 44 and Figure 45 show,
there is a constant delay between the edges of DACCLK and
DATACLK.
The DCLKPOL bit (Reg 02 Bit 4) allows the data to be latched
into the AD9786 on either the rising or falling edge of
DACCLK. With DCLKPOL = 0, the data is latched in on the
falling edge of DACCLK, as shown in Figure 44. With
DCLKPOL = 1, as shown in Figure 45, data is latched in on the
rising edge of DACCLK. The setup and hold times are always
with respect to the latching edge of DACCLK.
0
DACCLK
IN
DATACLK
OUT
DATA
t
t
D
= 6ns TYP
t
H
= 2.9ns MIN
t
S
= –0.5ns MIN
Figure 44. Data Timing, 1× Interpolation, DCLKPOL = 0
0
t
S
= –300ps TYP
t
H
= 2.9ns TYP
DACCLK
IN
DATA
Figure 45. Data Timing, 1× Interpolation, DCLKPOL = 1
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