參數(shù)資料
型號： AD9779ABSVZRL
廠商： Analog Devices Inc
文件頁數(shù)： 47/56頁
文件大?。?/td> 0K
描述： DAC 16BIT 1.0GSPS 100-TQFP
產品培訓模塊： Data Converter Fundamentals
DAC Architectures
設計資源： Interfacing ADL5370 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0016)
Interfacing ADL5371 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0017)
Interfacing ADL5372 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0018)
Interfacing ADL5373 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0019)
Interfacing ADL5374 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0020)
Interfacing ADL5375 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0021)
標準包裝： 1,000
位數(shù)： 16
數(shù)據(jù)接口： 串行
轉換器數(shù)目： 2
電壓電源： 模擬和數(shù)字
功率耗散（最大）： 300mW
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 100-TQFP 裸露焊盤
供應商設備封裝： 100-TQFP-EP（14x14）
包裝： 帶卷 (TR)
輸出數(shù)目和類型： 4 電流，單極
采樣率（每秒）： 1G
AD9776A/AD9778A/AD9779A
Rev. B | Page 51 of 56
POWER DISSIPATION
Figure 91 to Figure 99 show the power dissipation of the 1.8 V and 3.3 V digital and clock supplies in single DAC mode and dual DAC
mode. In addition to this, the power dissipation/current of the 3.3 V analog supply (mode and speed independent) in single DAC mode is
102 mW/31 mA. In dual DAC mode, this is 182 mW/55 mA. When the PLL is enabled, it adds 50 mA/90 mW to the 1.8 V clock supply.
0
250
fDATA (MSPS)
PO
W
E
R
(
W
)
0.6
0.7
0.5
0.4
0.3
0.2
0.1
25
50
75
100
125
150
175
200
225
8× INTERPOLATION,
ZERO STUFFING
8× INTERPOLATION
4× INTERPOLATION
4× INTERPOLATION,
ZERO STUFFING
2× INTERPOLATION
1× INTERPOLATION
2× INTERPOLATION,
ZERO STUFFING
1× INTERPOLATION,
ZERO STUFFING
06
45
2-
0
76
Figure 91. Total Power Dissipation, I Data Only, Real Mode
0
250
fDATA (MSPS)
PO
W
E
R
(
W
)
0.4
25
50
75
100
125
150
175
200
225
8× INTERPOLATION
4× INTERPOLATION
2× INTERPOLATION
1× INTERPOLATION
0.3
0.2
0.1
06
45
2-
0
78
Figure 92. Power Dissipation, Digital 1.8 V Supply, I Data Only, Real Mode,
Does Not Include Zero Stuffing
0
250
fDATA (MSPS)
PO
W
E
R
(
W
)
0.08
25
50
75
100
125
150
175
200
225
8× INTERPOLATION
4× INTERPOLATION
2× INTERPOLATION
1× INTERPOLATION
0.06
0.04
0.02
06
45
2-
0
79
Figure 93. Power Dissipation, Clock 1.8 V Supply, I Data Only, Real Mode,
Includes Modulation Modes, Does Not Include Zero Stuffing
0
250
fDATA (MSPS)
PO
W
E
R
(
W
)
0.075
25
50
75
100
125
150
175
200
225
0.050
0.025
ALL INTERPOLATION MODES
06
45
2-
0
80
Figure 94. Power Dissipation, Digital 3.3 V Supply, I Data Only, Real Mode,
Includes Modulation Modes and Zero Stuffing
0
300
250 275
fDATA (MSPS)
PO
W
ER
(
W
)
0.6
1.0
0.7
0.8
0.9
0.5
0.4
0.3
0.2
0.1
25
50
75
100 125 150 175 200 225
1× INTERPOLATION
1× INTERPOLATION,
ZERO STUFFING
2× INTERPOLATION,
ALL MODULATION MODES
2× INTERPOLATION,
ZERO STUFFING
4× INTERPOLATION,
ALL MODULATION
MODES
4× INTERPOLATION,
ZERO STUFFING
8× INTERPOLATION, ALL
MODULATION MODES
8× INTERPOLATION,
ZERO STUFFING
06
45
2-
0
77
Figure 95. Total Power Dissipation, Dual DAC Mode
0
250
fDATA (MSPS)
PO
W
E
R
(W
)
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
25
50
75
100
125
150
175
200
225
2× INTERPOLATION
4× INTERPOLATION
1× INTERPOLATION,
NO MODULATION
8× INTERPOLATION, fDAC/8,
fDAC/4,
fDAC/2,
NO MODULATION
06
45
2-
0
81
Figure 96. Power Dissipation, Digital 1.8 V Supply, I and Q Data, Dual DAC
Mode, Does Not Include Zero Stuffing
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相關代理商/技術參數(shù)
參數(shù)描述
AD9779A-DPG2-EBZ 功能描述:BOARD EVALUATION FOR AD9779A RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 數(shù)模轉換器 (DAC) 系列:* 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設置時間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581
AD9779A-EBZ 制造商:Analog Devices 功能描述:DUAL 16B, 1.0 GSPS TXDAC - Bulk
AD9779AMOD-EBZ 制造商:Analog Devices 功能描述:DUAL 16B, 1.0 GSPS TXDAC - Bulk
AD9779AXSVZ 制造商:Analog Devices 功能描述:DUAL 16-BIT, 1 GSPS, DIGITAL-TO-ANALOG CONVERTER - Bulk
AD9779BSV 制造商:Analog Devices 功能描述:DAC 2CH INTERPOLATION FLTR 16BIT 100TQFP EP - Bulk
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