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參數(shù)資料
| 型號： | AD9772AST |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | 14-Bit, 150 MSPS TxDAC⑩ with 2x Interpolation Filter |
| 中文描述： | PARALLEL, WORD INPUT LOADING, 0.011 us SETTLING TIME, 14-BIT DAC, PQFP48 |
| 封裝： | PLASTIC, LQFP-48 |
| 文件頁數(shù)： | 4/30頁 |
| 文件大?。?/td> | 340K |
| 代理商： | AD9772AST |
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REV. 0
–4–
AD9772–SPECIFICATIONS
DIGITAL SPECIFICATIONS
Parameter
(T
MIN
to T
MAX
, AVDD = +3 V, CLKVDD = +3 V, PLLVDD = +0 V, DVDD = +3 V, I
OUTFS
= 20 mA, unless
otherwise noted)
Min
Typ
Max
Units
DIGITAL INPUTS
Logic “1” Voltage
Logic “0” Voltage
Logic “1” Current
1
Logic “0” Current
Input Capacitance
2.1
3
0
V
V
μ
A
μ
A
pF
0.9
+10
+10
–10
–10
5
CLOCK INPUTS
Input Voltage Range
Common-Mode Voltage
Differential Voltage
0
0.75
0.5
3
2.25
V
V
V
1.5
1.5
PLL CLOCK ENABLED—FIGURE 1a
Input Setup Time (t
S
)
Input Hold Time (t
H
)
Latch Pulsewidth (t
LPW
)
1.0
2.5
1.5
ns
ns
ns
PLL CLOCK DISABLED—FIGURE 1b
Input Setup Time (t
S
)
Input Hold Time (t
H
)
Latch Pulsewidth (t
LPW
)
CLK/PLLLOCK Delay (t
OD
)
1.0
2.5
1.5
ns
ns
ns
ns
5
NOTES
1
MOD1 and MOD0 have typical input currents of 120
μ
A while SLEEP has a typical input current of 15
μ
A.
Specifications subject to change without notice.
t
S
0.025%
0.025%
DB0–DB13
CLK+ – CLK–
IOUTA
OR
IOUTB
t
H
t
LPW
t
PD
t
ST
Figure 1a. Timing Diagram—PLL Clock Multiplier Enabled
t
S
DB0–DB13
0.025%
0.025%
IOUTA
OR
IOUTB
t
OD
PLLLOCK
CLK+ – CLK–
t
H
t
LPW
t
PD
t
ST
Figure 1b. Timing Diagram—PLL Clock Multiplier Disabled
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| AD9773AST | 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit, 160 MSPS 2】/4】/8】 Interpolating Dual TxDAC+ D/A Converter |
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