參數(shù)資料
型號(hào)： AD9772AST
廠商： ANALOG DEVICES INC
元件分類： DAC
英文描述： 14-Bit, 150 MSPS TxDAC⑩ with 2x Interpolation Filter
中文描述： PARALLEL, WORD INPUT LOADING, 0.011 us SETTLING TIME, 14-BIT DAC, PQFP48
封裝： PLASTIC, LQFP-48
文件頁(yè)數(shù)： 17/30頁(yè)
文件大小： 340K
代理商： AD9772AST
REV. 0
AD9772
–17–
by a single-supply DAC or digital potentiometer, thus allowing
I
REF
to be digitally controlled for a fixed R
SET
. This particular
example shows the AD5220, an 8-bit serial input digital potenti-
ometer, along with the AD1580 voltage reference. Note, since
the input impedance of REFIO does interact and load the digi-
tal potentiometer wiper to create a slight nonlinearity in the
programmable voltage divider ratio, a digital potentiometer with
10 k
or less of resistance is recommended.
+1.2V REF
REFIO
FSADJ
CURRENT
SOURCE
ARRAY
250pF
REFLO
AVDD
AD9772
AD1580
+2.7 TO +3.6V
A
R
SET
10k
V
10k
V
AD5220
1.2V
Figure 34. Single-Supply Gain Control Circuit
ANALOG OUTPUTS
The AD9772 produces two complementary current outputs,
IOUTA and IOUTB, which may be configured for single-ended
or differential operation. IOUTA and IOUTB can be converted
into complementary single-ended voltage outputs, V
OUTA
and
V
OUTB
, via a load resistor, R
LOAD
, as described in the DAC
Transfer Function section, by Equations 5 through 8. The
differential voltage, V
DIFF
, existing between V
OUTA
and V
OUTB
,
can also be converted to a single-ended voltage via a transformer
or differential amplifier configuration.
Figure 35 shows the equivalent analog output circuit of the
AD9772, consisting of a parallel combination of PMOS differ-
ential current switches associated with each segmented current
source. The output impedance of IOUTA and IOUTB is deter-
mined by the equivalent parallel combination of the PMOS
switches and is typically 200
k
in parallel with 3 pF. Due to
the nature of a PMOS device, the output impedance is also
slightly dependent on the output voltage (i.e., V
OUTA
and V
OUTB
)
and, to a lesser extent, the analog supply voltage, AVDD, and
full-scale current, I
OUTFS
. Although the output impedance’s
signal dependency can be a source of dc nonlinearity and ac linear-
ity (i.e., distortion), its effects can be limited if certain precau-
tions are noted.
AD9772
AVDD
IOUTA
IOUTB
R
LOAD
R
LOAD
Figure 35. Equivalent Analog Output Circuit
IOUTA and IOUTB also have a negative and positive voltage
compliance range. The negative output compliance range of
–1.0 V is set by the breakdown limits of the CMOS process.
Operation beyond this maximum limit may result in a break-
down of the output stage and affect the reliability of the AD9772.
The positive output compliance range is slightly dependent on
the full-scale output current, I
OUTFS
. Operation beyond the
positive compliance range will induce clipping of the output
signal, which severely degrades the AD9772’s linearity and
distortion performance.
Operating the AD9772 with reduced voltage output swings at
IOUTA and IOUTB in a differential or single-ended output
configuration reduces the signal dependency of its output im-
pedance, thus enhancing distortion performance. Although the
voltage compliance range of IOUTA and IOUTB extends from
–1.0 V to +1.25 V, optimum distortion performance is achieved
when the maximum full-scale signal at IOUTA and IOUTB
does not exceed approximately 0.5 V. A properly selected trans-
former with a grounded center-tap will allow the AD9772 to
provide the required power and voltage levels to different loads
while maintaining reduced voltage swings at IOUTA and
IOUTB. DC-coupled applications requiring a differential or
single-ended output configuration should size R
LOAD
accord-
ingly. Refer to Applying the AD9772 section for examples of
various output configurations.
The most significant improvement in the AD9772’s distortion
and noise performance is realized using a differential output
configuration. The common-mode error sources of both IOUTA
and IOUTB can be substantially reduced by the common-mode
rejection of a transformer or differential amplifier. These
common-mode error sources include even-order distortion
products and noise. The enhancement in distortion performance
becomes more significant as the reconstructed waveform’s
frequency content increases and/or its amplitude decreases.
The distortion and noise performance of the AD9772 is also
dependent on the full-scale current setting, I
OUTFS
. Although
I
OUTFS
can be set between 2 mA and 20mA, selecting an I
OUTFS
of 20 mA will provide the best distortion and noise performance.
In summary, the AD9772 achieves the optimum distortion and
noise performance under the following conditions:
1. Positive voltage swing at IOUTA and IOUTB limited to
+0.5 V.
2. Differential Operation.
3. I
OUTFS
set to 20 mA.
4. PLL Clock Multiplier Disabled
Note the majority of the AC Characterization Curves for the
AD9772 are performed under the above-mentioned operating
conditions.
DIGITAL INPUTS/OUTPUTS
The AD9772 consists of several digital input pins used for data,
clock and control purposes. It also contains a single digital out-
put pin, PLLLOCK, used to monitor the status of the internal
PLL clock multiplier or provide a 1
×
clock output. The 14-bit
parallel data inputs follow standard positive binary coding where
DB13 is the most significant bit (MSB), and DB0 is the least
significant bit (LSB). IOUTA produces a full-scale output
current when all data bits are at Logic 1. IOUTB produces a
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