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參數(shù)資料
| 型號(hào)： | AD9761-EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 21/24頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD9761 |
| 產(chǎn)品培訓(xùn)模塊： | DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | TxDAC® |
| DAC 的數(shù)量： | 2 |
| 位數(shù)： | 10 |
| 采樣率（每秒）： | 40M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 設(shè)置時(shí)間： | 35ns |
| DAC 型： | 電流 |
| 工作溫度： | -40°C ~ 85°C |
| 已供物品： | 板 |
| 已用 IC / 零件： | AD9761 |
| 相關(guān)產(chǎn)品： | AD9761ARSZRL-ND - IC DAC 10BIT DUAL 40MSPS 28-SSOP AD9761ARSZ-ND - IC DAC 10BIT DUAL 40MSPS 28-SSOP AD9761ARSRL-ND - IC DAC 10BIT DUAL 40MSPS 28-SSOP AD9761ARS-ND - IC DAC 10BIT DUAL 40MSPS 28-SSOP |
AD9761
–6–
AD9761
–7–
PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic
Description
1
DB9
Most Significant Data Bit (MSB).
2–9
DB8–DB1
Data Bits 1–8.
10
DB0
Least Significant Data Bit (LSB).
11
CLOCK
Clock Input. Both DACs’ outputs updated on positive edge of clock and digital filters read respective
input registers.
12
WRITE
Write Input. DAC input registers latched on positive edge of write.
13
SELECT
Select Input. Select high routes input data to I DAC; select low routes data to Q DAC.
14
DVDD
Digital Supply Voltage (2.7 V to 5.5 V).
15
DCOM
Digital Common.
16
COMP3
Internal Bias Node for Switch Driver Circuitry. Decouple to ACOM with 0.1 F capacitor.
17
QOUTA
Q DAC Current Output. Full-scale current when all data bits are 1s.
18
QOUTB
Q DAC Complementary Current Output. Full-scale current when all data bits are 0s.
19
REFLO
Reference Ground when Internal 1.2 V Reference Used. Connect to AVDD to disable internal reference.
20
REFIO
Reference Input/Output. Serves as reference input when internal reference disabled. Serves as 1.2 V
reference output when internal reference activated. Requires 0.1 F capacitor to ACOM when internal
reference activated.
21
FSADJ
Full-Scale Current Output Adjust. Resistance to ACOM sets full-scale output current.
22
COMP2
Bandwidth/Noise Reduction Node. Add 0.1 F to AVDD for optimum performance.
23
AVDD
Analog Supply Voltage (3 V to 5.5 V).
24
ACOM
Analog Common.
25
IOUTB
I DAC Complementary Current Output. Full-scale current when all data bits are 0s.
26
IOUTA
I DAC Current Output. Full-scale current when all data bits are 1s.
27
COMP1
Internal Bias Node for Switch Driver Circuitry. Decouple to AGND with 0.1 F capacitor.
28
RESET/SLEEP
Power-Down Control Input if Asserted for Four Clock Cycles or Longer. Reset control input if
asserted for less than four clock cycles. Active high. Connect to DCOM if not used. Refer to RESET/
SLEEP Mode Operation section.
PIN CONFIGURATION
14
13
12
11
17
16
15
20
19
18
10
9
8
1
2
3
4
7
6
5
TOP VIEW
(Not to Scale)
28
27
26
25
24
23
22
21
AD9761
(MSB) DB9
IOUTB
IOUTA
COMP1
RESET/SLEEP
DB8
DB7
DB6
COMP2
AVDD
ACOM
DB5
DB4
DB3
DB2
DB1
(LSB) DB0
REFLO
REFIO
FSADJ
CLOCK
WRITE
SELECT
DVDD
QOUTB
DCOM
COMP3
QOUTA
REV. C
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