參數(shù)資料
型號(hào)： AD9739A-FMC-EBZ
廠商： Analog Devices Inc
文件頁數(shù)： 41/64頁
文件大小： 0K
描述： BOARD EVAL W/FMC CONN FPGA DEV
設(shè)計(jì)資源： AD9739A-FMC-EBZ Gerber Files
AD9739A-FMC-EBZ Layout
標(biāo)準(zhǔn)包裝： 1
系列： TxDAC®
DAC 的數(shù)量： 1
位數(shù)： 14
采樣率（每秒）： 2.5G
數(shù)據(jù)接口： 串行，SPI?
DAC 型： 電流
工作溫度： -40°C ~ 85°C
已供物品： 板
已用 IC / 零件： AD9739A
AD9737A/AD9739A
Data Sheet
Rev. | Page 46 of 64
CLK INPUT COMMON MODE
Table 23. CLK Input Common Mode Register (CROSS_CNT1 and CROSS_CNT2)
Address
(Hex)
Bit Name
Bits
R/W
Default
Setting
Description
0x22
DIR_P
4
R/W
0x0
DIR_P and DIR_N.
0 = VCM at the DACCLK_P input decreases with the offset value.
1 = VCM at the DACCLK_P input increases with the offset value.
CLKx_OFFSET sets the magnitude of the offset for the DACCLK_P and
DACCLK_N inputs. For optimum performance, set to 1111.
CLKP_OFFSET[3:0]
[3:0]
R/W
0x0000
0x23
DIR_N
4
R/W
0x0
CLKN_OFFSET[3:0]
[3:0]
R/W
0x0000
MU CONTROLLER CONFIGURATION AND STATUS
Table 24. Mu Controller Configuration and Status Register (PHS_DET, MU_DUTY, MU_CNT[1:4], and MU_STAT1)
Address
(Hex)
Bit Name
Bits
R/W
Default
Setting
Description
0x24
CMP_BST
5
R/W
0x0
Phase detector enable and boost bias bits.
Note that both bits should always be set to 1 to enable these functions.
PHS_DET
AUTO_EN
4
R/W
0x0
0x25
MU_
DUTYAUTO_EN
7
R/W
0x0
Mu controller duty cycle enable.
Note that this bit should always be set to 1 to enable.
0x26
Slope
6
R/W
0x1
Mu controller phase slope lock. 0 = negative slope, 1 = positive slope. Note
that a setting of 0 is recommended for best ac performance.
Mode[1:0]
[5:4]
R/W
0x00
Sets the Mu controller mode of operation.
00 = search and track (recommended).
01 = search only.
10 = track.
Read
3
R/W
0x0
Set to 1 to read the current value of the Mu delay line in.
Gain[1:0]
[2:1]
R/W
0x01
Sets the Mu controller tracking gain.
Recommended to leave at the default 01 setting.
Enable
0
R/W
0x0
0 = enable the Mu controller.
1 = disable the Mu controller.
0x27
MUDEL[0]
7
R/W
0x0
The LSB of the 9-bit MUDEL setting.
SRCH_MODE[1:0]
[6:5]
R/W
0x0
Sets the direction in which the Mu controller searches (from its initial MUDEL
setting) for the optimum Mu delay line setting that corresponds to the desired
phase/slope setting (that is, SET_PHS and slope ).
00 = down.
01 = up.
10 = down/up (recommended).
SET_PHS[4:0]
[4:0]
R/W
0x0
Sets the target phase that the Mu controller locks to with a maximum setting
of 16.
A setting of 4 (that is, 00100) is recommended for optimum ac performance.
0x28
MUDEL[8:1]
[7:0]
W
0x00
With enable (Bit 0, Register 0x26) set to 0, this 9-bit value represents the
value that the Mu delay is set to. Note that the maximum value is 432.
With enable set to 1, this value represents the Mu delay value at which the
controller begins its search. Setting this value to the delay line midpoint of
216 is recommended.
R
0x00
When read (Bit 3, Register 0x26) is set to 1, the value read back is equal to
the value written into the register when enable = 0 or the value that the
Mu controller locks to when enable = 1.
0x29
SEARCH_TOL
7
R/W
0x0
0 = not exact (can find a phase within two values of the desired phase).
1 = finds the exact phase that is targeted (optimal setting).
Retry
6
R/W
0x0
0 = stop the search if the correct value is not found,
1 = retry the search if the correct value is not found.
CONTRST
5
R/W
0x0
Controls whether the controller resets or continues when it does not find
the desired phase.
0 = continue (optimal setting), 1 = reset.
C
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